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---------------------------------------------------------------------------
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-- (c) 2014 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_misc.all;
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ENTITY avalon_atari_dma IS
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PORT
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(
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CLK : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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-- avalon signals
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CHIPSELECT : IN STD_LOGIC;
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ADDRESS : IN STD_LOGIC_VECTOR(21 downto 0);
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READ: IN STD_LOGIC;
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READDATA : OUT STD_LOGIC_VECTOR(31 downto 0);
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WRITE : IN STD_LOGIC;
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WRITEDATA : IN STD_LOGIC_VECTOR(31 downto 0);
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BYTEENABLE : IN STD_LOGIC_VECTOR(3 downto 0);
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WAITREQUEST : OUT STD_LOGIC;
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-- atari dma signals
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DMA_FETCH : OUT STD_LOGIC;
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DMA_READ_ENABLE : OUT STD_LOGIC;
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DMA_32BIT_WRITE_ENABLE : OUT STD_LOGIC; -- cough, width for read or writes...
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DMA_8BIT_WRITE_ENABLE : OUT STD_LOGIC;
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DMA_ADDR : OUT STD_LOGIC_VECTOR(23 downto 0);
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DMA_WRITE_DATA : OUT STD_LOGIC_VECTOR(31 downto 0);
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MEMORY_READY_DMA : IN STD_LOGIC;
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DMA_MEMORY_DATA : IN STD_LOGIC_VECTOR(31 downto 0)
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);
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END avalon_atari_dma;
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ARCHITECTURE vhdl OF avalon_atari_dma IS
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SIGNAL BYTE_ADDRESS : STD_LOGIC_VECTOR(1 downto 0);
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SIGNAL SPECIAL_MEM : STD_LOGIC;
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SIGNAL DMA_MEMORY_DATA_LOW : STD_LOGIC_VECTOR(7 downto 0);
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BEGIN
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DMA_FETCH <= (READ or WRITE) and CHIPSELECT;
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DMA_READ_ENABLE <= READ;
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DMA_ADDR <= ADDRESS&BYTE_ADDRESS;
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WAITREQUEST <= NOT(MEMORY_READY_DMA) or not(RESET_N);
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process(ADDRESS)
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begin
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special_mem <= '0';
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-- $00000-$0FFFF = Own ROM/RAM
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-- $10000-$1FFFF = Atari
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-- $20000-$2FFFF = Atari - savestate (gtia/antic/pokey have memory behind them)
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if (or_reduce(std_logic_vector(ADDRESS(21 downto 19))) = '0') then -- special area
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special_mem <= ADDRESS(15);
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end if;
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end process;
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process(SPECIAL_MEM, DMA_MEMORY_DATA)
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begin
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DMA_MEMORY_DATA_LOW <= DMA_MEMORY_DATA(7 downto 0);
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if (SPECIAL_MEM = '1') then
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DMA_MEMORY_DATA_LOW <= DMA_MEMORY_DATA(15 downto 8);
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end if;
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end process;
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process(BYTEENABLE, DMA_MEMORY_DATA_LOW, WRITEDATA, SPECIAL_MEM)
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begin
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BYTE_ADDRESS <= "00";
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DMA_8BIT_WRITE_ENABLE <= '0';
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DMA_32BIT_WRITE_ENABLE <= '0';
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READDATA <= DMA_MEMORY_DATA;
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DMA_WRITE_DATA <= WRITEDATA;
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case BYTEENABLE is
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when "0001" =>
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DMA_8BIT_WRITE_ENABLE <= '1';
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READDATA <= DMA_MEMORY_DATA_LOW&DMA_MEMORY_DATA_LOW&DMA_MEMORY_DATA_LOW&DMA_MEMORY_DATA_LOW;
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DMA_WRITE_DATA <= x"000000"&WRITEDATA(7 downto 0);
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when "0010" =>
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BYTE_ADDRESS <= "01";
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DMA_8BIT_WRITE_ENABLE <= '1';
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READDATA <= DMA_MEMORY_DATA_LOW&DMA_MEMORY_DATA_LOW&DMA_MEMORY_DATA_LOW&DMA_MEMORY_DATA_LOW;
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DMA_WRITE_DATA <= x"000000"&WRITEDATA(15 downto 8);
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when "0100" =>
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BYTE_ADDRESS <= "10";
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DMA_8BIT_WRITE_ENABLE <= '1';
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READDATA <= DMA_MEMORY_DATA_LOW&DMA_MEMORY_DATA_LOW&DMA_MEMORY_DATA_LOW&DMA_MEMORY_DATA_LOW;
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DMA_WRITE_DATA <= x"000000"&WRITEDATA(23 downto 16);
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when "1000" =>
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BYTE_ADDRESS <= "11";
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DMA_8BIT_WRITE_ENABLE <= '1';
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READDATA <= DMA_MEMORY_DATA_LOW&DMA_MEMORY_DATA_LOW&DMA_MEMORY_DATA_LOW&DMA_MEMORY_DATA_LOW;
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DMA_WRITE_DATA <= x"000000"&WRITEDATA(31 downto 24);
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when "1111" =>
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DMA_32BIT_WRITE_ENABLE <= '1';
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when others =>
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-- invalid
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end case;
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end process;
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END vhdl;
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