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---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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LIBRARY work;
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ENTITY atari5200core_mcc IS
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GENERIC
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(
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TV : integer; -- 1 = PAL, 0=NTSC
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VIDEO : integer; -- 1 = SVIDEO, 2 = VGA
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SCANDOUBLE : integer; -- 1 = YES, 0=NO, (+ later scanlines etc)
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internal_rom : integer;
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internal_ram : integer;
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ext_clock : integer
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);
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PORT
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(
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FPGA_CLK : IN STD_LOGIC;
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-- For test bench
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EXT_CLK_SDRAM : in std_logic_vector(ext_clock downto 1);
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EXT_CLK : in std_logic_vector(ext_clock downto 1);
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EXT_SDRAM_CLK : in std_logic_vector(ext_clock downto 1);
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EXT_SVIDEO_DAC_CLK : in std_logic_vector(ext_clock downto 1);
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EXT_SCANDOUBLE_CLK : in std_logic_vector(ext_clock downto 1);
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EXT_PLL_LOCKED : in std_logic_vector(ext_clock downto 1);
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PS2K_CLK : IN STD_LOGIC;
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PS2K_DAT : IN STD_LOGIC;
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PS2M_CLK : IN STD_LOGIC;
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PS2M_DAT : IN STD_LOGIC;
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VGA_VS : OUT STD_LOGIC;
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VGA_HS : OUT STD_LOGIC;
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VGA_B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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VGA_G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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VGA_R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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JOY1_n : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
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JOY2_n : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
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AUDIO_L : OUT std_logic;
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AUDIO_R : OUT std_logic;
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SDRAM_BA : OUT STD_LOGIC_VECTOR(1 downto 0);
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SDRAM_CS_N : OUT STD_LOGIC;
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SDRAM_RAS_N : OUT STD_LOGIC;
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SDRAM_CAS_N : OUT STD_LOGIC;
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SDRAM_WE_N : OUT STD_LOGIC;
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SDRAM_DQM_n : OUT STD_LOGIC_vector(1 downto 0);
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SDRAM_CLK : OUT STD_LOGIC;
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--SDRAM_CKE : OUT STD_LOGIC;
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SDRAM_A : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
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SDRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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SD_DAT0 : IN STD_LOGIC;
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SD_CLK : OUT STD_LOGIC;
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SD_CMD : OUT STD_LOGIC;
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SD_DAT3 : OUT STD_LOGIC;
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USB2_P : INOUT STD_LOGIC;
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USB2_N : INOUT STD_LOGIC
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);
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END atari5200core_mcc;
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ARCHITECTURE vhdl OF atari5200core_mcc IS
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component hq_dac
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port (
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reset :in std_logic;
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clk :in std_logic;
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clk_ena : in std_logic;
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pcm_in : in std_logic_vector(19 downto 0);
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dac_out : out std_logic
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);
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end component;
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COMPONENT sdram_ctrl
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port
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(
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--//--------------------
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--// Clocks and reset --
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--//--------------------
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--// Global reset
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rst : in std_logic;
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--// Controller clock
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clk : in std_logic;
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--// Sequencer cycles
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seq_cyc : in std_logic_vector(11 downto 0);
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--// Sequencer phase
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seq_ph : in std_logic;
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--// Refresh cycle
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refr_cyc : in std_logic;
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--//------------------------
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--// Access port #1 (CPU) --
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--//------------------------
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--// RAM select
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ap1_ram_sel : in std_logic;
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--// Address bus
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ap1_address : in std_logic_vector(23 downto 1);
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--// Read enable
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ap1_rden : in std_logic;
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--// Write enable
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ap1_wren : in std_logic;
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--// Byte enable
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ap1_bena : in std_logic_vector(1 downto 0);
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--// Data bus (read)
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ap1_rddata : out std_logic_vector(15 downto 0);
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--// Data bus (write)
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ap1_wrdata : in std_logic_vector(15 downto 0);
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--// Burst size
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ap1_bst_siz : in std_logic_vector(2 downto 0);
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--// Read burst active
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ap1_rd_bst_act : out std_logic;
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--// Write burst active
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ap1_wr_bst_act : out std_logic;
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--//------------------------
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--// Access port #2 (GPU) --
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--//------------------------
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--// RAM select
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ap2_ram_sel : in std_logic;
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--// Address bus
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ap2_address : in std_logic_vector(23 downto 1);
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--// Read enable
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ap2_rden : in std_logic;
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--// Write enable
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ap2_wren : in std_logic;
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--// Byte enable
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ap2_bena : in std_logic_vector(1 downto 0);
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--// Data bus (read)
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ap2_rddata : out std_logic_vector(15 downto 0);
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--// Data bus (write)
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ap2_wrdata : in std_logic_vector(15 downto 0);
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--// Burst size
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ap2_bst_siz : in std_logic_vector(2 downto 0);
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--// Read burst active
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ap2_rd_bst_act : out std_logic;
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--// Write burst active
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ap2_wr_bst_act : out std_logic;
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--//------------------------
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--// Access port #3 (CTL) --
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--//------------------------
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--// RAM select
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ap3_ram_sel : in std_logic;
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--// Address bus
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ap3_address : in std_logic_vector(23 downto 1);
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--// Read enable
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ap3_rden : in std_logic;
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--// Write enable
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ap3_wren : in std_logic;
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--// Byte enable
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ap3_bena : in std_logic_vector(1 downto 0);
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--// Data bus (read)
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ap3_rddata : out std_logic_vector(15 downto 0);
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--// Data bus (write)
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ap3_wrdata : in std_logic_vector(15 downto 0);
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--// Burst size
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ap3_bst_siz : in std_logic_vector(2 downto 0);
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--// Read burst active
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ap3_rd_bst_act : out std_logic;
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--// Write burst active
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ap3_wr_bst_act : out std_logic;
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--//------------------------
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--// SDRAM memory signals --
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--//------------------------
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--// SDRAM controller ready
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sdram_rdy : out std_logic;
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--// SDRAM chip select
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sdram_cs_n : out std_logic;
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--// SDRAM row address strobe
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sdram_ras_n : out std_logic;
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--// SDRAM column address strobe
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sdram_cas_n : out std_logic;
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--// SDRAM write enable
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sdram_we_n : out std_logic;
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--// SDRAM DQ masks
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sdram_dqm_n : out std_logic_vector(1 downto 0);
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--// SDRAM bank address
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sdram_ba : out std_logic_vector(1 downto 0);
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--// SDRAM address
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sdram_addr : out std_logic_vector(11 downto 0);
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--// SDRAM data
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sdram_dq_oe : out std_logic;
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sdram_dq_o : out std_logic_vector(15 downto 0);
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sdram_dq_i : in std_logic_vector(15 downto 0)
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);
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END COMPONENT;
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signal AUDIO_L_PCM : std_logic_vector(15 downto 0);
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signal AUDIO_R_PCM : std_logic_vector(15 downto 0);
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signal VIDEO_VS : std_logic;
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signal VIDEO_HS : std_logic;
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signal VIDEO_CS : std_logic;
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signal VIDEO_R : std_logic_vector(7 downto 0);
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signal VIDEO_G : std_logic_vector(7 downto 0);
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signal VIDEO_B : std_logic_vector(7 downto 0);
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signal VIDEO_BLANK : std_logic;
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signal VIDEO_BURST : std_logic;
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signal VIDEO_START_OF_FIELD : std_logic;
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signal VIDEO_ODD_LINE : std_logic;
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signal JOY1_USB : std_logic_vector(5 downto 0);
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signal JOY2_USB : std_logic_vector(5 downto 0);
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signal JOY1_USB_N : std_logic_vector(5 downto 0);
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signal JOY2_USB_N : std_logic_vector(5 downto 0);
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signal JOY1_IN_N : std_logic_vector(5 downto 0);
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signal JOY2_IN_N : std_logic_vector(5 downto 0);
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signal JOY1_BOTH_n : std_logic_vector(5 downto 0);
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signal JOY2_BOTH_n : std_logic_vector(5 downto 0);
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signal PLL1_LOCKED : std_logic;
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signal CLK_PLL1 : std_logic;
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signal RESET_n : std_logic;
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signal PLL_LOCKED : std_logic;
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signal CLK : std_logic;
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signal CLK_SDRAM : std_logic;
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-- SDRAM
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signal PREREG_SDRAM_REQUEST : std_logic;
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signal PREREG_SDRAM_READ_ENABLE : STD_LOGIC;
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signal PREREG_SDRAM_WRITE_ENABLE : std_logic;
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signal PREREG_SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);
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SIGNAL PREREG_SDRAM_DI : std_logic_vector(31 downto 0);
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SIGNAL PREREG_SDRAM_WIDTH_32BIT_ACCESS : std_logic;
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SIGNAL PREREG_SDRAM_WIDTH_16BIT_ACCESS : std_logic;
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SIGNAL PREREG_SDRAM_WIDTH_8BIT_ACCESS : std_logic;
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signal SDRAM_REQUEST : std_logic;
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signal SDRAM_READ_ENABLE : STD_LOGIC;
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signal SDRAM_WRITE_ENABLE : std_logic;
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signal SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);
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SIGNAL SDRAM_DI : std_logic_vector(31 downto 0);
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SIGNAL SDRAM_WIDTH_32BIT_ACCESS : std_logic;
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SIGNAL SDRAM_WIDTH_16BIT_ACCESS : std_logic;
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SIGNAL SDRAM_WIDTH_8BIT_ACCESS : std_logic;
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signal SDRAM_REQUEST_COMPLETE : std_logic;
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signal SDRAM_REFRESH : std_logic;
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signal SYSTEM_RESET_REQUEST: std_logic;
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signal seq_reg : std_logic_vector(11 downto 0);
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signal seq_next : std_logic_vector(11 downto 0);
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signal seq_ph_reg : std_logic;
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signal seq_ph_next : std_logic;
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signal ref_reg : std_logic;
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signal ref_next : std_logic;
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signal sdram_request_complete_next : std_logic;
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signal sdram_request_complete_reg : std_logic;
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signal sdram_request_next : std_logic;
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signal sdram_request_reg : std_logic;
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signal ram_di_next : std_logic_vector(15 downto 0);
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signal ram_di_reg : std_logic_vector(15 downto 0);
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signal ram_do_next : std_logic_vector(31 downto 0);
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signal ram_do_reg : std_logic_vector(31 downto 0);
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signal ram_do : std_logic_vector(15 downto 0);
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signal ram_bena_next : std_logic_vector(1 downto 0);
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signal ram_bena_reg : std_logic_vector(1 downto 0);
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signal ram_rd_active : std_logic;
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signal ram_wr_active : std_logic;
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signal sdram_dq_oe : std_logic;
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signal sdram_dq_o : std_logic_vector(15 downto 0);
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signal sdram_dq_i : std_logic_vector(15 downto 0);
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signal sdram_rdy : std_logic;
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signal sdram_reset_ctrl_n_next : std_logic;
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signal sdram_reset_ctrl_n_reg : std_logic;
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signal sdram_reset_n_next : std_logic;
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signal sdram_reset_n_reg : std_logic;
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-- pokey keyboard
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SIGNAL KEYBOARD_SCAN : std_logic_vector(5 downto 0);
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SIGNAL KEYBOARD_RESPONSE : std_logic_vector(1 downto 0);
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signal controller_select : std_logic_vector(1 downto 0);
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-- gtia consol keys
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SIGNAL FKEYS : std_logic_vector(11 downto 0);
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-- scandoubler
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signal scandouble_clk : std_logic;
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signal half_scandouble_enable_reg : std_logic;
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signal half_scandouble_enable_next : std_logic;
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signal scanlines_reg : std_logic;
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signal scanlines_next : std_logic;
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function palette_from_scandouble( scandouble : integer ) return integer is
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begin
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if (scandouble = 1) then
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return 0;
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else
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return 1;
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end if;
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end palette_from_scandouble;
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-- svideo
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signal svideo_dac_clk : std_logic;
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signal svideo_y : std_logic_vector(7 downto 0);
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signal svideo_c : std_logic_vector(5 downto 0);
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-- dma/virtual drive
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signal DMA_ADDR_FETCH : std_logic_vector(23 downto 0);
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signal DMA_WRITE_DATA : std_logic_vector(31 downto 0);
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signal DMA_FETCH : std_logic;
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signal DMA_32BIT_WRITE_ENABLE : std_logic;
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signal DMA_16BIT_WRITE_ENABLE : std_logic;
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signal DMA_8BIT_WRITE_ENABLE : std_logic;
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signal DMA_READ_ENABLE : std_logic;
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signal DMA_MEMORY_READY : std_logic;
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signal DMA_MEMORY_DATA : std_logic_vector(31 downto 0);
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signal ZPU_ADDR_ROM : std_logic_vector(15 downto 0);
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signal ZPU_ROM_DATA : std_logic_vector(31 downto 0);
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signal ZPU_OUT1 : std_logic_vector(31 downto 0);
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signal ZPU_OUT2 : std_logic_vector(31 downto 0);
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signal ZPU_OUT3 : std_logic_vector(31 downto 0);
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signal ZPU_OUT4 : std_logic_vector(31 downto 0);
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signal ZPU_OUT5 : std_logic_vector(31 downto 0);
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signal zpu_pokey_enable : std_logic;
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signal zpu_sio_txd : std_logic;
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signal zpu_sio_rxd : std_logic;
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signal zpu_sio_command : std_logic;
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-- system control from zpu
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signal ram_select : std_logic_vector(2 downto 0);
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signal reset_atari : std_logic;
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signal pause_atari : std_logic;
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SIGNAL speed_6502 : std_logic_vector(5 downto 0);
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-- usb
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signal CLK_USB : std_logic;
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signal USBWireVPin : std_logic;
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signal USBWireVMin : std_logic;
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signal USBWireVPout : std_logic;
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signal USBWireVMout : std_logic;
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signal USBWireOE_n : std_logic;
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signal PS2_KEYS : STD_LOGIC_VECTOR(511 downto 0);
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signal PS2_KEYS_NEXT : STD_LOGIC_VECTOR(511 downto 0);
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-- paddles
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signal JOY1X : std_logic_vector(7 downto 0);
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signal JOY1Y : std_logic_vector(7 downto 0);
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signal JOY2X : std_logic_vector(7 downto 0);
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signal JOY2Y : std_logic_vector(7 downto 0);
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BEGIN
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USB2_N <= USBWireVPout when USBWireOE_n='0' else 'Z';
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USB2_P <= USBWireVMout when USBWireOE_n='0' else 'Z';
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USBWireVPin <= USB2_N;
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USBWireVMin <= USB2_P;
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dac_left : hq_dac
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port map
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(
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reset => not(reset_n),
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clk => clk,
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clk_ena => '1',
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pcm_in => AUDIO_L_PCM&"0000",
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dac_out => audio_l
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);
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dac_right : hq_dac
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port map
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(
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reset => not(reset_n),
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clk => clk,
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clk_ena => '1',
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pcm_in => AUDIO_R_PCM&"0000",
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dac_out => audio_r
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);
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gen_fake_pll : if ext_clock=1 generate
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CLK_SDRAM <= EXT_CLK_SDRAM(1);
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CLK <= EXT_CLK(1);
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SDRAM_CLK <= EXT_CLK_SDRAM(1);
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SVIDEO_DAC_CLK <= EXT_SVIDEO_DAC_CLK(1);
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SCANDOUBLE_CLK <= EXT_SCANDOUBLE_CLK(1);
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PLL_LOCKED <= EXT_PLL_LOCKED(1);
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end generate;
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usb_pll : entity work.usbpll
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PORT MAP(inclk0 => FPGA_CLK,
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c0 => CLK_USB,
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locked => open);
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gen_real_pll : if ext_clock=0 generate
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gen_tv_ntsc : if tv=0 generate
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mcc_pll : entity work.ntsc_pll
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PORT MAP(inclk0 => FPGA_CLK,
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c0 => CLK_PLL1,
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locked => PLL1_LOCKED);
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mcc_pll2 : entity work.pll_downstream_ntsc
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PORT MAP(inclk0 => CLK_PLL1,
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c0 => CLK_SDRAM,
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c1 => CLK,
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c2 => SDRAM_CLK,
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c3 => SVIDEO_DAC_CLK,
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c4 => SCANDOUBLE_CLK,
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areset => not(PLL1_LOCKED),
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locked => PLL_LOCKED);
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end generate;
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end generate;
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reset_n <= PLL_LOCKED;
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-- PS2 to pokey
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keyboard_map1 : entity work.ps2_to_atari5200
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GENERIC MAP
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(
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ps2_enable => 1,
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direct_enable => 1
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)
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PORT MAP
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(
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CLK => clk,
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RESET_N => reset_n,
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PS2_CLK => ps2k_clk,
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PS2_DAT => ps2k_dat,
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INPUT => zpu_out4,
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FIRE2 => '0'&'0'¬(JOY2_BOTH_N(4)&JOY1_BOTH_N(4)),
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CONTROLLER_SELECT => CONTROLLER_SELECT, -- selected stick keyboard/shift button
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KEYBOARD_SCAN => KEYBOARD_SCAN,
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KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
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FKEYS => FKEYS,
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PS2_KEYS_NEXT_OUT => ps2_keys_next,
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PS2_KEYS => ps2_keys
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);
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JOY1_IN_N <= JOY1_n(4)&JOY1_n(5)&JOY1_n(0)&JOY1_n(1)&JOY1_n(2)&JOY1_n(3);
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JOY2_IN_N <= JOY2_n(4)&JOY2_n(5)&JOY2_n(0)&JOY2_n(1)&JOY2_n(2)&JOY2_n(3);
|
|
|
|
JOY1_USB <= zpu_out2(5 downto 4)&zpu_out2(0)&zpu_out2(1)&zpu_out2(2)&zpu_out2(3);
|
|
JOY2_USB <= zpu_out3(5 downto 4)&zpu_out3(0)&zpu_out3(1)&zpu_out3(2)&zpu_out3(3);
|
|
JOY1_USB_N <= not(JOY1_USB);
|
|
JOY2_USB_N <= not(JOY2_USB);
|
|
|
|
JOY1_BOTH_N <= JOY1_IN_N and JOY1_USB_N;
|
|
JOY2_BOTH_N <= JOY2_IN_N and JOY2_USB_N;
|
|
|
|
JOY1X <= zpu_out5(7 downto 0);
|
|
JOY1Y <= zpu_out5(15 downto 8);
|
|
JOY2X <= zpu_out5(23 downto 16);
|
|
JOY2Y <= zpu_out5(31 downto 24);
|
|
|
|
return_to_boot_menu : entity work.delayed_reconfig
|
|
PORT MAP
|
|
(
|
|
CLK_5MHZ => FPGA_CLK,
|
|
RESET_N => RESET_N,
|
|
RECONFIG_BUTTON => (FKEYS(1) or FKEYS(4))
|
|
);
|
|
|
|
atari5200_simple_sdram1 : entity work.atari5200core_simplesdram
|
|
GENERIC MAP
|
|
(
|
|
cycle_length => 16,
|
|
internal_rom => internal_rom,
|
|
internal_ram => internal_ram,
|
|
video_bits => 8,
|
|
palette => palette_from_scandouble(scandouble)
|
|
)
|
|
PORT MAP
|
|
(
|
|
CLK => CLK,
|
|
--RESET_N => RESET_N and SDRAM_RESET_N and not(SYSTEM_RESET_REQUEST),
|
|
RESET_N => RESET_N and SDRAM_RESET_N_REG,
|
|
|
|
VIDEO_VS => VIDEO_VS,
|
|
VIDEO_HS => VIDEO_HS,
|
|
VIDEO_CS => VIDEO_CS,
|
|
VIDEO_B => VIDEO_B,
|
|
VIDEO_G => VIDEO_G,
|
|
VIDEO_R => VIDEO_R,
|
|
VIDEO_BLANK =>VIDEO_BLANK,
|
|
VIDEO_BURST =>VIDEO_BURST,
|
|
VIDEO_START_OF_FIELD =>VIDEO_START_OF_FIELD,
|
|
VIDEO_ODD_LINE =>VIDEO_ODD_LINE,
|
|
|
|
AUDIO_L => AUDIO_L_PCM,
|
|
AUDIO_R => AUDIO_R_PCM,
|
|
|
|
SDRAM_REQUEST => PREREG_SDRAM_REQUEST,
|
|
SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
|
|
SDRAM_READ_ENABLE => PREREG_SDRAM_READ_ENABLE,
|
|
SDRAM_WRITE_ENABLE => PREREG_SDRAM_WRITE_ENABLE,
|
|
SDRAM_ADDR => PREREG_SDRAM_ADDR,
|
|
SDRAM_DO => ram_do_reg,
|
|
SDRAM_DI => PREREG_SDRAM_DI,
|
|
SDRAM_32BIT_WRITE_ENABLE => PREREG_SDRAM_WIDTH_32bit_ACCESS,
|
|
SDRAM_16BIT_WRITE_ENABLE => PREREG_SDRAM_WIDTH_16bit_ACCESS,
|
|
SDRAM_8BIT_WRITE_ENABLE => PREREG_SDRAM_WIDTH_8bit_ACCESS,
|
|
SDRAM_REFRESH => SDRAM_REFRESH,
|
|
|
|
DMA_FETCH => dma_fetch,
|
|
DMA_READ_ENABLE => dma_read_enable,
|
|
DMA_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
|
|
DMA_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
|
|
DMA_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
|
|
DMA_ADDR => dma_addr_fetch,
|
|
DMA_WRITE_DATA => dma_write_data,
|
|
MEMORY_READY_DMA => dma_memory_ready,
|
|
DMA_MEMORY_DATA => dma_memory_data,
|
|
|
|
THROTTLE_COUNT_6502 => speed_6502,
|
|
HALT => pause_atari,
|
|
|
|
-- JOYSTICK
|
|
JOY1_X => signed(joy1x),
|
|
JOY1_Y => signed(joy1y),
|
|
JOY1_N => JOY1_BOTH_N(5)&JOY1_BOTH_N(3 downto 0),
|
|
JOY2_X => signed(joy2x),
|
|
JOY2_Y => signed(joy2y),
|
|
JOY2_N => JOY2_BOTH_N(5)&JOY2_BOTH_N(3 downto 0),
|
|
|
|
-- Pokey keyboard matrix
|
|
-- Standard component available to connect this to PS2
|
|
KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
|
|
KEYBOARD_SCAN => KEYBOARD_SCAN,
|
|
CONTROLLER_SELECT => CONTROLLER_SELECT
|
|
);
|
|
|
|
process(clk_sdram,sdram_reset_ctrl_n_reg)
|
|
begin
|
|
if (sdram_reset_ctrl_n_reg='0') then
|
|
seq_reg <= "010000000000";
|
|
seq_ph_reg <= '1';
|
|
ref_reg <= '0';
|
|
|
|
ram_do_reg <= (others=>'0');
|
|
ram_di_reg <= (others=>'0');
|
|
ram_bena_reg <= (others=>'0');
|
|
sdram_request_complete_reg <= '0';
|
|
sdram_request_reg <= '0';
|
|
elsif (clk_sdram'event and clk_sdram = '1') then
|
|
seq_reg <= seq_next;
|
|
seq_ph_reg <= seq_ph_next;
|
|
ref_reg <= ref_next;
|
|
|
|
ram_do_reg <= ram_do_next;
|
|
ram_di_reg <= ram_di_next;
|
|
ram_bena_reg <= ram_bena_next;
|
|
sdram_request_complete_reg <= sdram_request_complete_next;
|
|
sdram_request_reg <= sdram_request_next;
|
|
end if;
|
|
end process;
|
|
|
|
process(clk,reset_n)
|
|
begin
|
|
if (reset_n='0') then
|
|
sdram_reset_n_reg <= '0';
|
|
sdram_reset_ctrl_n_reg <= '0';
|
|
elsif (clk'event and clk = '1') then
|
|
sdram_reset_n_reg <= sdram_reset_n_next;
|
|
sdram_reset_ctrl_n_reg <= reset_n;
|
|
end if;
|
|
end process;
|
|
|
|
-- Generate sdram sequence
|
|
process(seq_reg, seq_ph_reg, ref_reg)
|
|
begin
|
|
seq_next <= seq_reg(10 downto 0)&seq_reg(11);
|
|
seq_ph_next <= seq_ph_reg;
|
|
ref_next <= ref_reg;
|
|
if (seq_reg(11) = '1') then
|
|
seq_ph_next <= not(seq_ph_reg);
|
|
ref_next <= not(ref_reg);
|
|
end if;
|
|
end process;
|
|
|
|
process(seq_reg, seq_next, sdram_rdy, sdram_reset_n_reg, reset_atari)
|
|
begin
|
|
sdram_reset_n_next <= sdram_reset_n_reg;
|
|
if (sdram_rdy = '1' and seq_next(7)='1' and seq_reg(7)='0') then
|
|
sdram_reset_n_next <= '1';
|
|
end if;
|
|
if (reset_atari = '1') then
|
|
sdram_reset_n_next <= '0';
|
|
end if;
|
|
end process;
|
|
|
|
-- register sdram request on the falling edge, 1/3 timing not enough, but 1/2 timing should be... This pushes back request 1 clock cycle. Result can also be clocking on the falling edge!
|
|
process(clk,reset_n)
|
|
begin
|
|
if (reset_n='0') then
|
|
SDRAM_REQUEST <= '0';
|
|
SDRAM_READ_ENABLE <= '0';
|
|
SDRAM_WRITE_ENABLE <= '0';
|
|
SDRAM_ADDR <= (others=>'0');
|
|
SDRAM_DI <= (others=>'0');
|
|
SDRAM_WIDTH_32BIT_ACCESS <= '0';
|
|
SDRAM_WIDTH_16BIT_ACCESS <= '0';
|
|
SDRAM_WIDTH_8BIT_ACCESS <= '0';
|
|
elsif(clk'event and clk='0') then -- FALLING EDGE
|
|
SDRAM_REQUEST <= PREREG_SDRAM_REQUEST;
|
|
SDRAM_READ_ENABLE <= PREREG_SDRAM_READ_ENABLE;
|
|
SDRAM_WRITE_ENABLE <= PREREG_SDRAM_WRITE_ENABLE;
|
|
SDRAM_ADDR <= PREREG_SDRAM_ADDR;
|
|
SDRAM_DI <= PREREG_SDRAM_DI;
|
|
SDRAM_WIDTH_32BIT_ACCESS <= PREREG_SDRAM_WIDTH_32BIT_ACCESS;
|
|
SDRAM_WIDTH_16BIT_ACCESS <= PREREG_SDRAM_WIDTH_16BIT_ACCESS;
|
|
SDRAM_WIDTH_8BIT_ACCESS <= PREREG_SDRAM_WIDTH_8BIT_ACCESS;
|
|
end if;
|
|
end process;
|
|
|
|
-- Adapt SDRAM
|
|
process(sdram_request_reg, sdram_request, sdram_request_complete_reg, ram_do_reg, seq_reg, ram_do, ram_rd_active, ram_wr_active, SDRAM_WIDTH_8BIT_ACCESS, SDRAM_WRITE_ENABLE, SDRAM_READ_ENABLE, SDRAM_DI, SDRAM_ADDR)
|
|
begin
|
|
sdram_request_next <= (sdram_request_reg or sdram_request) and not(sdram_request_complete_reg);
|
|
sdram_request_complete_next <= sdram_request_complete_reg;
|
|
ram_bena_next <= "00";
|
|
ram_di_next <= (others=>'0');
|
|
ram_do_next <= ram_do_reg;
|
|
|
|
case seq_reg is
|
|
when "000000000001" =>
|
|
-- nop
|
|
when "000000000010" => -- write data from next...
|
|
if (SDRAM_WRITE_ENABLE = '1') then
|
|
if (SDRAM_WIDTH_8BIT_ACCESS = '1') then
|
|
ram_di_next <= SDRAM_DI(7 downto 0)&SDRAM_DI(7 downto 0);
|
|
ram_bena_next <= SDRAM_ADDR(0)¬(SDRAM_ADDR(0));
|
|
else
|
|
ram_di_next <= SDRAM_DI(15 downto 0);
|
|
ram_bena_next <= "11";
|
|
end if;
|
|
end if;
|
|
when "000000000100" =>
|
|
if (SDRAM_WRITE_ENABLE = '1') then
|
|
if (SDRAM_WIDTH_8BIT_ACCESS = '1') then
|
|
ram_di_next <= (others=>'0');
|
|
else
|
|
ram_di_next <= SDRAM_DI(31 downto 16);
|
|
ram_bena_next <= "11";
|
|
end if;
|
|
end if;
|
|
if ((ram_wr_active)='1') then
|
|
sdram_request_complete_next <= '1';
|
|
sdram_request_next <= '0';
|
|
end if;
|
|
when "000000001000" =>
|
|
-- nop
|
|
when "000000010000" =>
|
|
-- nop
|
|
when "000000100000" =>
|
|
sdram_request_complete_next <= '0';
|
|
-- nop
|
|
when "000001000000" =>
|
|
if (SDRAM_READ_ENABLE = '1') then
|
|
if (SDRAM_WIDTH_8BIT_ACCESS = '1') then
|
|
if (SDRAM_ADDR(0) = '0') then
|
|
ram_do_next(15 downto 0) <= ram_do(7 downto 0)&ram_do(7 downto 0);
|
|
else
|
|
ram_do_next(15 downto 0) <= ram_do(15 downto 8)&ram_do(15 downto 8);
|
|
end if;
|
|
else
|
|
ram_do_next(15 downto 0) <= ram_do;
|
|
end if;
|
|
end if;
|
|
when "000010000000" =>
|
|
if (SDRAM_READ_ENABLE = '1') then
|
|
if (SDRAM_WIDTH_8BIT_ACCESS = '1') then
|
|
ram_do_next(31 downto 16) <= (others=>'0');
|
|
else
|
|
ram_do_next(31 downto 16) <= ram_do;
|
|
end if;
|
|
end if;
|
|
if ((ram_rd_active)='1') then
|
|
sdram_request_complete_next <= '1';
|
|
sdram_request_next <= '0';
|
|
end if;
|
|
when "000100000000" =>
|
|
-- nop
|
|
when "001000000000" =>
|
|
-- nop
|
|
when "010000000000" =>
|
|
-- nop
|
|
when "100000000000" =>
|
|
sdram_request_complete_next <= '0';
|
|
-- nop
|
|
when others =>
|
|
-- never
|
|
end case;
|
|
end process;
|
|
|
|
SDRAM_REQUEST_COMPLETE <= SDRAM_REQUEST_COMPLETE_REG;
|
|
sdram_controller : sdram_ctrl
|
|
PORT MAP
|
|
(
|
|
CLK => CLK_SDRAM,
|
|
rst => not(sdram_reset_ctrl_n_reg),
|
|
seq_cyc => seq_reg(11 downto 0),
|
|
seq_ph => seq_ph_reg,
|
|
--refr_cyc => ref_reg,
|
|
refr_cyc => SDRAM_REFRESH,
|
|
|
|
ap1_ram_sel => SDRAM_REQUEST_NEXT,
|
|
ap1_address => '0'&SDRAM_ADDR(22 downto 1),
|
|
ap1_rden => SDRAM_READ_ENABLE,
|
|
ap1_wren => SDRAM_WRITE_ENABLE,
|
|
ap1_bena => ram_bena_reg,
|
|
ap1_rddata => ram_do,
|
|
ap1_wrdata => ram_di_reg,
|
|
ap1_bst_siz => "001",
|
|
ap1_rd_bst_act => ram_rd_active,
|
|
ap1_wr_bst_act => ram_wr_active,
|
|
|
|
ap2_ram_sel => '0',
|
|
ap2_address => "00000000000000000000000",
|
|
ap2_rden => '0',
|
|
ap2_wren => '0',
|
|
ap2_bena => "11",
|
|
ap2_rddata => open,
|
|
ap2_wrdata => X"0000",
|
|
ap2_bst_siz => "111",
|
|
ap2_rd_bst_act => open,
|
|
ap2_wr_bst_act => open,
|
|
|
|
ap3_ram_sel => '0',
|
|
ap3_address => "00000000000000000000000",
|
|
ap3_rden => '0',
|
|
ap3_wren => '0',
|
|
ap3_bena => "11",
|
|
ap3_rddata => open,
|
|
ap3_wrdata => X"0000",
|
|
ap3_bst_siz => "111",
|
|
ap3_rd_bst_act => open,
|
|
ap3_wr_bst_act => open,
|
|
|
|
sdram_rdy => sdram_rdy,
|
|
sdram_cs_n => sdram_cs_n,
|
|
sdram_ras_n => sdram_ras_n,
|
|
sdram_cas_n => sdram_cas_n,
|
|
sdram_we_n => sdram_we_n,
|
|
sdram_dqm_n => sdram_dqm_n,
|
|
sdram_ba => sdram_ba,
|
|
sdram_addr => sdram_a(11 downto 0),
|
|
sdram_dq_oe => sdram_dq_oe,
|
|
sdram_dq_o => sdram_dq_o,
|
|
sdram_dq_i => sdram_dq_i
|
|
);
|
|
|
|
sdram_dq <= sdram_dq_o when sdram_dq_oe='1' else (others=>'Z');
|
|
sdram_dq_i <= sdram_dq;
|
|
sdram_a(12) <= '1';
|
|
|
|
-- Video options
|
|
gen_video_vga : if video=2 generate
|
|
gen_scandouble_off: if scandouble=0 generate
|
|
VGA_HS <= not(VIDEO_CS);
|
|
VGA_VS <= '1';
|
|
VGA_B <= VIDEO_B(7 downto 4);
|
|
VGA_G <= VIDEO_G(7 downto 4);
|
|
VGA_R <= VIDEO_R(7 downto 4);
|
|
end generate;
|
|
|
|
gen_scandouble_on: if scandouble=1 generate
|
|
scanlines_next <= scanlines_reg xor (not(ps2_keys(16#11#)) and ps2_keys_next(16#11#)); -- left alt
|
|
process(scandouble_clk,sdram_reset_n_reg)
|
|
begin
|
|
if (sdram_reset_n_reg='0') then
|
|
half_scandouble_enable_reg <= '0';
|
|
scanlines_reg <= '0';
|
|
elsif (scandouble_clk'event and scandouble_clk='1') then
|
|
half_scandouble_enable_reg <= half_scandouble_enable_next;
|
|
scanlines_reg <= scanlines_next;
|
|
end if;
|
|
end process;
|
|
|
|
half_scandouble_enable_next <= not(half_scandouble_enable_reg);
|
|
|
|
scandoubler1: entity work.scandoubler
|
|
PORT MAP
|
|
(
|
|
CLK => SCANDOUBLE_CLK,
|
|
RESET_N => sdram_reset_n_reg,
|
|
|
|
VGA => '1',
|
|
COMPOSITE_ON_HSYNC => '0', -- TODO
|
|
|
|
colour_enable => half_scandouble_enable_reg,
|
|
doubled_enable => '1',
|
|
scanlines_on => scanlines_reg,
|
|
|
|
-- GTIA interface
|
|
pal => '0',
|
|
colour_in => VIDEO_B,
|
|
vsync_in => VIDEO_VS,
|
|
hsync_in => VIDEO_HS,
|
|
csync_in => VIDEO_CS,
|
|
|
|
-- TO TV...
|
|
R => VGA_R,
|
|
G => VGA_G,
|
|
B => VGA_B,
|
|
|
|
VSYNC => VGA_VS,
|
|
HSYNC => VGA_HS
|
|
);
|
|
end generate;
|
|
|
|
end generate;
|
|
|
|
gen_video_svideo: if video=1 generate
|
|
|
|
-- SVIDEO COMPONENT
|
|
svideo : entity work.svideo
|
|
PORT MAP
|
|
(
|
|
areset_n => RESET_N,
|
|
ecs_clk => CLK,
|
|
dac_clk => SVIDEO_DAC_CLK,
|
|
r_in => VIDEO_R,
|
|
g_in => VIDEO_G,
|
|
b_in => VIDEO_B,
|
|
sof => VIDEO_VS, -- base on vsync?
|
|
vpos_lsb => VIDEO_ODD_LINE,
|
|
blank => VIDEO_BLANK,
|
|
burst => VIDEO_BURST,
|
|
csync_n => not(VIDEO_CS),
|
|
|
|
y_out => svideo_y,
|
|
c_out => svideo_c,
|
|
|
|
pal_ntsc => not('0')
|
|
);
|
|
VGA_B <= svideo_y(7 downto 4);
|
|
VGA_G <= svideo_y(3 downto 0);
|
|
VGA_R <= svideo_c(5 downto 2);
|
|
VGA_HS <= svideo_c(1);
|
|
VGA_VS <= svideo_c(0);
|
|
|
|
end generate;
|
|
|
|
zpu: entity work.zpucore
|
|
GENERIC MAP
|
|
(
|
|
platform => 1,
|
|
spi_clock_div => 1, -- 28MHz/2. Max for SD cards is 25MHz...
|
|
memory => 8192,
|
|
usb => 1,
|
|
nMHz_clock_div => 48
|
|
)
|
|
PORT MAP
|
|
(
|
|
-- standard...
|
|
CLK => CLK,
|
|
RESET_N => RESET_N and sdram_rdy,
|
|
|
|
-- dma bus master (with many waitstates...)
|
|
ZPU_ADDR_FETCH => dma_addr_fetch,
|
|
ZPU_DATA_OUT => dma_write_data,
|
|
ZPU_FETCH => dma_fetch,
|
|
ZPU_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
|
|
ZPU_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
|
|
ZPU_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
|
|
ZPU_READ_ENABLE => dma_read_enable,
|
|
ZPU_MEMORY_READY => dma_memory_ready,
|
|
ZPU_MEMORY_DATA => dma_memory_data,
|
|
|
|
-- rom bus master
|
|
-- data on next cycle after addr
|
|
ZPU_ADDR_ROM => zpu_addr_rom,
|
|
ZPU_ROM_DATA => zpu_rom_data,
|
|
|
|
-- spi master
|
|
-- Too painful to bit bang spi from zpu, so we have a hardware master in here
|
|
ZPU_SPI_DI => sd_dat0,
|
|
ZPU_SPI_CLK => sd_clk,
|
|
ZPU_SPI_DO => sd_cmd,
|
|
ZPU_SPI_SELECT0 => sd_dat3,
|
|
ZPU_SPI_SELECT1 => open,
|
|
|
|
-- SIO
|
|
-- Ditto for speaking to Atari, we have a built in Pokey
|
|
ZPU_POKEY_ENABLE => zpu_pokey_enable,
|
|
ZPU_SIO_TXD => zpu_sio_txd,
|
|
ZPU_SIO_RXD => zpu_sio_rxd,
|
|
ZPU_SIO_COMMAND => zpu_sio_command,
|
|
ZPU_SIO_CLK => '0',
|
|
|
|
-- external control
|
|
-- switches etc. sector DMA blah blah.
|
|
ZPU_IN1 => X"000"&
|
|
"00"&ps2_keys(16#76#)&ps2_keys(16#5A#)&ps2_keys(16#174#)&ps2_keys(16#16B#)&ps2_keys(16#172#)&ps2_keys(16#175#)& -- (esc)FLRDU
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FKEYS,
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ZPU_IN2 => X"00000000",
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ZPU_IN3 => X"00000000",
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ZPU_IN4 => X"00000000",
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|
|
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-- ouputs - e.g. Atari system control, halt, throttle, rom select
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ZPU_OUT1 => zpu_out1,
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ZPU_OUT2 => zpu_out2, --joy0
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|
ZPU_OUT3 => zpu_out3, --joy1
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|
ZPU_OUT4 => zpu_out4, --keyboard
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|
ZPU_OUT5 => zpu_out5, --analog stick
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|
|
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-- USB host
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CLK_nMHz => CLK_USB,
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CLK_USB => CLK_USB,
|
|
|
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USBWireVPin(0) => USBWireVPin,
|
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USBWireVMin(0) => USBWireVMin,
|
|
USBWireVPout(0) => USBWireVPout,
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USBWireVMout(0) => USBWireVMout,
|
|
USBWireOE_n(0) => USBWireOE_n
|
|
);
|
|
|
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pause_atari <= zpu_out1(0);
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reset_atari <= zpu_out1(1);
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|
speed_6502 <= zpu_out1(7 downto 2);
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|
ram_select <= zpu_out1(10 downto 8);
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|
|
|
zpu_rom1: entity work.zpu_rom
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|
port map(
|
|
clock => clk,
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|
address => zpu_addr_rom(14 downto 2),
|
|
q => zpu_rom_data
|
|
);
|
|
|
|
enable_179_clock_div_zpu_pokey : entity work.enable_divider
|
|
generic map (COUNT=>16) -- cycle_length
|
|
port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>zpu_pokey_enable);
|
|
|
|
END vhdl;
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