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-- megafunction wizard: %ALTCLKCTRL%
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-- GENERATION: STANDARD
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-- VERSION: WM1.0
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-- MODULE: altclkctrl
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-- ============================================================
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-- File Name: clkctrl.vhd
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-- Megafunction Name(s):
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-- altclkctrl
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--
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-- Simulation Library Files(s):
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-- cycloneive
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-- ============================================================
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-- ************************************************************
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-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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--
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-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
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-- ************************************************************
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--Copyright (C) 1991-2013 Altera Corporation
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--Your use of Altera Corporation's design tools, logic functions
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--and other software and tools, and its AMPP partner logic
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--functions, and any output files from any of the foregoing
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--(including device programming or simulation files), and any
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--associated documentation or information are expressly subject
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--to the terms and conditions of the Altera Program License
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--Subscription Agreement, Altera MegaCore Function License
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--Agreement, or other applicable license agreement, including,
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--without limitation, that your use is for the sole purpose of
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--programming logic devices manufactured by Altera and sold by
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--Altera or its authorized distributors. Please refer to the
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--applicable agreement for further details.
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--altclkctrl CBX_AUTO_BLACKBOX="ALL" CLOCK_TYPE="Global Clock" DEVICE_FAMILY="Cyclone IV E" ENA_REGISTER_MODE="falling edge" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" clkselect ena inclk outclk
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--VERSION_BEGIN 13.0 cbx_altclkbuf 2013:06:12:18:04:00:SJ cbx_cycloneii 2013:06:12:18:04:00:SJ cbx_lpm_add_sub 2013:06:12:18:04:00:SJ cbx_lpm_compare 2013:06:12:18:04:00:SJ cbx_lpm_decode 2013:06:12:18:04:00:SJ cbx_lpm_mux 2013:06:12:18:04:00:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:04:00:SJ cbx_stratixii 2013:06:12:18:04:00:SJ cbx_stratixiii 2013:06:12:18:04:00:SJ cbx_stratixv 2013:06:12:18:04:00:SJ VERSION_END
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LIBRARY cycloneive;
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USE cycloneive.all;
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--synthesis_resources = clkctrl 1
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY clkctrl_altclkctrl_7ji IS
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PORT
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(
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clkselect : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
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ena : IN STD_LOGIC := '1';
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inclk : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
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outclk : OUT STD_LOGIC
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);
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END clkctrl_altclkctrl_7ji;
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ARCHITECTURE RTL OF clkctrl_altclkctrl_7ji IS
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SIGNAL wire_clkctrl1_outclk : STD_LOGIC;
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SIGNAL clkselect_wire : STD_LOGIC_VECTOR (1 DOWNTO 0);
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SIGNAL inclk_wire : STD_LOGIC_VECTOR (3 DOWNTO 0);
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COMPONENT cycloneive_clkctrl
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GENERIC
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(
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clock_type : STRING;
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ena_register_mode : STRING := "falling edge";
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lpm_type : STRING := "cycloneive_clkctrl"
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);
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PORT
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(
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clkselect : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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ena : IN STD_LOGIC;
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inclk : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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outclk : OUT STD_LOGIC
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);
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END COMPONENT;
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BEGIN
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clkselect_wire <= ( clkselect);
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inclk_wire <= ( inclk);
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outclk <= wire_clkctrl1_outclk;
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clkctrl1 : cycloneive_clkctrl
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GENERIC MAP (
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clock_type => "Global Clock",
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ena_register_mode => "falling edge"
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)
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PORT MAP (
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clkselect => clkselect_wire,
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ena => ena,
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inclk => inclk_wire,
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outclk => wire_clkctrl1_outclk
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);
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END RTL; --clkctrl_altclkctrl_7ji
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--VALID FILE
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY clkctrl IS
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PORT
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(
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ena : IN STD_LOGIC := '1';
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inclk : IN STD_LOGIC ;
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outclk : OUT STD_LOGIC
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);
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END clkctrl;
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ARCHITECTURE RTL OF clkctrl IS
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SIGNAL sub_wire0 : STD_LOGIC ;
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SIGNAL sub_wire1_bv : BIT_VECTOR (1 DOWNTO 0);
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SIGNAL sub_wire1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
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SIGNAL sub_wire2 : STD_LOGIC ;
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SIGNAL sub_wire3 : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL sub_wire4_bv : BIT_VECTOR (2 DOWNTO 0);
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SIGNAL sub_wire4 : STD_LOGIC_VECTOR (2 DOWNTO 0);
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COMPONENT clkctrl_altclkctrl_7ji
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PORT (
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clkselect : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
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ena : IN STD_LOGIC ;
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inclk : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
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outclk : OUT STD_LOGIC
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);
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END COMPONENT;
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BEGIN
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sub_wire1_bv(1 DOWNTO 0) <= "00";
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sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
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sub_wire4_bv(2 DOWNTO 0) <= "000";
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sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
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outclk <= sub_wire0;
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sub_wire2 <= inclk;
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sub_wire3 <= sub_wire4(2 DOWNTO 0) & sub_wire2;
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clkctrl_altclkctrl_7ji_component : clkctrl_altclkctrl_7ji
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PORT MAP (
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clkselect => sub_wire1,
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ena => ena,
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inclk => sub_wire3,
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outclk => sub_wire0
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);
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END RTL;
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-- ============================================================
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-- CNX file retrieval info
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-- ============================================================
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-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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-- Retrieval info: PRIVATE: clock_inputs NUMERIC "1"
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-- Retrieval info: CONSTANT: ENA_REGISTER_MODE STRING "falling edge"
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-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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-- Retrieval info: CONSTANT: USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION STRING "OFF"
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-- Retrieval info: CONSTANT: clock_type STRING "Global Clock"
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-- Retrieval info: USED_PORT: ena 0 0 0 0 INPUT VCC "ena"
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-- Retrieval info: USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk"
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-- Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk"
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-- Retrieval info: CONNECT: @clkselect 0 0 2 0 GND 0 0 2 0
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-- Retrieval info: CONNECT: @ena 0 0 0 0 ena 0 0 0 0
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-- Retrieval info: CONNECT: @inclk 0 0 3 1 GND 0 0 3 0
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-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 0 0
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-- Retrieval info: CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0
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-- Retrieval info: GEN_FILE: TYPE_NORMAL clkctrl.vhd TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL clkctrl.inc FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL clkctrl.cmp TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL clkctrl.bsf FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL clkctrl_inst.vhd FALSE
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-- Retrieval info: LIB_FILE: cycloneive
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