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component pll_acore is
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port (
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refclk : in std_logic := 'X'; -- clk
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rst : in std_logic := 'X'; -- reset
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outclk_0 : out std_logic; -- clk
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outclk_1 : out std_logic; -- clk
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outclk_2 : out std_logic; -- clk
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outclk_3 : out std_logic; -- clk
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locked : out std_logic; -- export
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reconfig_to_pll : in std_logic_vector(63 downto 0) := (others => 'X'); -- reconfig_to_pll
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reconfig_from_pll : out std_logic_vector(63 downto 0) -- reconfig_from_pll
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);
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end component pll_acore;
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