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repo2/eclaireXL_ITX/hardware/test/test_hdmi/pll2.cmp

component pll2 is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
outclk_1 : out std_logic; -- clk
locked : out std_logic -- export
);
end component pll2;

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