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component clkctrl2 is
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port (
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inclk3x : in std_logic := 'X'; -- inclk3x
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inclk2x : in std_logic := 'X'; -- inclk2x
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inclk1x : in std_logic := 'X'; -- inclk1x
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inclk0x : in std_logic := 'X'; -- inclk0x
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clkselect : in std_logic_vector(1 downto 0) := (others => 'X'); -- clkselect
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outclk : out std_logic -- outclk
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);
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end component clkctrl2;
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