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component clkctrl2 is
port (
inclk3x : in std_logic := 'X'; -- inclk3x
inclk2x : in std_logic := 'X'; -- inclk2x
inclk1x : in std_logic := 'X'; -- inclk1x
inclk0x : in std_logic := 'X'; -- inclk0x
clkselect : in std_logic_vector(1 downto 0) := (others => 'X'); -- clkselect
outclk : out std_logic -- outclk
);
end component clkctrl2;

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