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---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY sync_switches IS
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PORT (
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CLK : IN STD_LOGIC;
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SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
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KEY : IN STD_LOGIC_VECTOR(3 downto 0);
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SYNC_KEYS : out std_logic_vector(3 downto 0);
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SYNC_SWITCHES : out std_logic_vector(9 downto 0)
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);
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END sync_switches;
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ARCHITECTURE Behavior OF sync_switches IS
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component synchronizer IS
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PORT
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(
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CLK : IN STD_LOGIC;
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RAW : IN STD_LOGIC;
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SYNC : OUT STD_LOGIC
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);
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END component;
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signal sw_reg : std_logic_vector(9 downto 0);
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signal key_reg : std_logic_vector(3 downto 0);
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BEGIN
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sw9_synchronizer : synchronizer
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port map (clk=>clk, raw=>sw(9), sync=>sw_reg(9));
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sw8_synchronizer : synchronizer
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port map (clk=>clk, raw=>sw(8), sync=>sw_reg(8));
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sw7_synchronizer : synchronizer
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port map (clk=>clk, raw=>sw(7), sync=>sw_reg(7));
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sw6_synchronizer : synchronizer
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port map (clk=>clk, raw=>sw(6), sync=>sw_reg(6));
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sw5_synchronizer : synchronizer
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port map (clk=>clk, raw=>sw(5), sync=>sw_reg(5));
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sw4_synchronizer : synchronizer
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port map (clk=>clk, raw=>sw(4), sync=>sw_reg(4));
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sw3_synchronizer : synchronizer
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port map (clk=>clk, raw=>sw(3), sync=>sw_reg(3));
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sw2_synchronizer : synchronizer
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port map (clk=>clk, raw=>sw(2), sync=>sw_reg(2));
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sw1_synchronizer : synchronizer
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port map (clk=>clk, raw=>sw(1), sync=>sw_reg(1));
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sw0_synchronizer : synchronizer
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port map (clk=>clk, raw=>sw(0), sync=>sw_reg(0));
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key3_synchronizer : synchronizer
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port map (clk=>clk, raw=>not(key(3)), sync=>key_reg(3));
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key2_synchronizer : synchronizer
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port map (clk=>clk, raw=>not(key(2)), sync=>key_reg(2));
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key1_synchronizer : synchronizer
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port map (clk=>clk, raw=>not(key(1)), sync=>key_reg(1));
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key0_synchronizer : synchronizer
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port map (clk=>clk, raw=>not(key(0)), sync=>key_reg(0));
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-- outputs
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SYNC_KEYS <= key_reg(3)&key_reg(2)&key_reg(1)&key_reg(0);
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SYNC_SWITCHES <= sw_reg(9)&sw_reg(8)&sw_reg(7)&sw_reg(6)&sw_reg(5)&sw_reg(4)&sw_reg(3)&sw_reg(2)&sw_reg(1)&sw_reg(0);
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END Behavior;
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