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---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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LIBRARY work;
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ENTITY atari5200core_de1 IS
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GENERIC
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(
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TV : integer -- 1 = PAL, 0=NTSC
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);
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PORT
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(
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CLOCK_50 : IN STD_LOGIC;
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AUD_BCLK : IN STD_LOGIC;
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AUD_DACLRCK : IN STD_LOGIC;
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I2C_SCLK : INOUT STD_LOGIC;
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I2C_SDAT : INOUT STD_LOGIC;
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PS2_CLK : IN STD_LOGIC;
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PS2_DAT : IN STD_LOGIC;
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UART_RXD : IN STD_LOGIC;
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UART_TXD : OUT STD_LOGIC;
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GPIO_0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
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GPIO_1 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
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KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
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AUD_XCK : OUT STD_LOGIC;
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AUD_DACDAT : OUT STD_LOGIC;
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FL_OE_N : OUT STD_LOGIC;
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FL_WE_N : OUT STD_LOGIC;
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FL_RST_N : OUT STD_LOGIC;
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FL_ADDR : OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
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FL_DQ : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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SRAM_CE_N : OUT STD_LOGIC;
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SRAM_OE_N : OUT STD_LOGIC;
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SRAM_WE_N : OUT STD_LOGIC;
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SRAM_LB_N : OUT STD_LOGIC;
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SRAM_UB_N : OUT STD_LOGIC;
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SRAM_ADDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
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SRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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DRAM_BA_0 : OUT STD_LOGIC;
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DRAM_BA_1 : OUT STD_LOGIC;
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DRAM_CS_N : OUT STD_LOGIC;
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DRAM_RAS_N : OUT STD_LOGIC;
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DRAM_CAS_N : OUT STD_LOGIC;
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DRAM_WE_N : OUT STD_LOGIC;
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DRAM_LDQM : OUT STD_LOGIC;
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DRAM_UDQM : OUT STD_LOGIC;
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DRAM_CLK : OUT STD_LOGIC;
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DRAM_CKE : OUT STD_LOGIC;
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DRAM_ADDR : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
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DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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SD_CLK : OUT STD_LOGIC;
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SD_CMD : OUT STD_LOGIC;
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SD_THREE : OUT STD_LOGIC;
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SD_DATA : IN STD_LOGIC;
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HEX0 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
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HEX1 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
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HEX2 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
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HEX3 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
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LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
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VGA_VS : OUT STD_LOGIC;
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VGA_HS : OUT STD_LOGIC;
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VGA_B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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VGA_G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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VGA_R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
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);
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END atari5200core_de1;
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ARCHITECTURE vhdl OF atari5200core_de1 IS
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-- SYSTEM
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SIGNAL CLK : STD_LOGIC;
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SIGNAL CLK_SDRAM : STD_LOGIC;
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SIGNAL RESET_N : STD_LOGIC;
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signal SDRAM_RESET_N : std_logic;
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SIGNAL PLL_LOCKED : STD_LOGIC;
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-- GTIA
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signal CONSOL_OUT : std_logic_vector(3 downto 0);
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signal CONSOL_IN : std_logic_vector(3 downto 0);
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signal GTIA_TRIG : std_logic_vector(3 downto 0);
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-- CARTRIDGE ACCESS
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--SIGNAL CART_RD4 : STD_LOGIC;
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--SIGNAL CART_RD5 : STD_LOGIC;
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--SIGNAL CART_S4_n : STD_LOGIC;
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--SIGNAL CART_S5_n : STD_LOGIC;
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--SIGNAL CART_CCTL_n : STD_LOGIC;
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-- PBI
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SIGNAL PBI_WRITE_DATA : std_logic_vector(31 downto 0);
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SIGNAL PBI_WIDTH_32BIT_ACCESS : std_logic;
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SIGNAL PBI_WIDTH_16BIT_ACCESS : std_logic;
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SIGNAL PBI_WIDTH_8BIT_ACCESS : std_logic;
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-- INTERNAL ROM/RAM
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SIGNAL RAM_ADDR : STD_LOGIC_VECTOR(18 DOWNTO 0);
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SIGNAL RAM_DO : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL RAM_REQUEST : STD_LOGIC;
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SIGNAL RAM_REQUEST_COMPLETE : STD_LOGIC;
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SIGNAL RAM_WRITE_ENABLE : STD_LOGIC;
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SIGNAL ROM_ADDR : STD_LOGIC_VECTOR(21 DOWNTO 0);
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SIGNAL ROM_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL ROM_REQUEST : STD_LOGIC;
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SIGNAL ROM_REQUEST_COMPLETE : STD_LOGIC;
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-- SDRAM
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signal SDRAM_REQUEST : std_logic;
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signal SDRAM_REQUEST_COMPLETE : std_logic;
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signal SDRAM_READ_ENABLE : STD_LOGIC;
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signal SDRAM_WRITE_ENABLE : std_logic;
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signal SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);
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signal SDRAM_DO : STD_LOGIC_VECTOR(31 DOWNTO 0);
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signal SDRAM_REFRESH : std_logic;
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-- pokey keyboard
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SIGNAL KEYBOARD_SCAN : std_logic_vector(5 downto 0);
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SIGNAL KEYBOARD_RESPONSE : std_logic_vector(1 downto 0);
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-- SIO
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SIGNAL SIO_RXD : std_logic;
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SIGNAL SIO_COMMAND : std_logic;
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SIGNAL SIO_TXD : std_logic;
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SIGNAL GPIO_SIO_RXD : std_logic;
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-- VIDEO
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signal VGA_VS_RAW : std_logic;
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signal VGA_HS_RAW : std_logic;
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signal VGA_CS_RAW : std_logic;
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-- AUDIO
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signal AUDIO_LEFT : std_logic_vector(15 downto 0);
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signal AUDIO_RIGHT : std_logic_vector(15 downto 0);
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-- dma/virtual drive
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signal DMA_ADDR_FETCH : std_logic_vector(23 downto 0);
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signal DMA_WRITE_DATA : std_logic_vector(31 downto 0);
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signal DMA_FETCH : std_logic;
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signal DMA_32BIT_WRITE_ENABLE : std_logic;
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signal DMA_16BIT_WRITE_ENABLE : std_logic;
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signal DMA_8BIT_WRITE_ENABLE : std_logic;
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signal DMA_READ_ENABLE : std_logic;
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signal DMA_MEMORY_READY : std_logic;
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signal DMA_MEMORY_DATA : std_logic_vector(31 downto 0);
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signal ZPU_ADDR_ROM : std_logic_vector(15 downto 0);
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signal ZPU_ROM_DATA : std_logic_vector(31 downto 0);
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signal ZPU_OUT1 : std_logic_vector(31 downto 0);
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signal ZPU_OUT2 : std_logic_vector(31 downto 0);
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signal ZPU_OUT3 : std_logic_vector(31 downto 0);
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signal ZPU_OUT4 : std_logic_vector(31 downto 0);
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signal zpu_pokey_enable : std_logic;
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signal zpu_sio_txd : std_logic;
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signal zpu_sio_rxd : std_logic;
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signal zpu_sio_command : std_logic;
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SIGNAL FKEYS : std_logic_vector(11 downto 0);
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-- system control from zpu
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signal reset_atari : std_logic;
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signal pause_atari : std_logic;
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SIGNAL speed_6502 : std_logic_vector(5 downto 0);
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-- GPIO
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signal GPIO_0_DIR_OUT : std_logic_vector(35 downto 0);
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signal GPIO_0_OUT : std_logic_vector(35 downto 0);
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signal GPIO_1_DIR_OUT : std_logic_vector(35 downto 0);
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signal GPIO_1_OUT : std_logic_vector(35 downto 0);
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signal TRIGGERS : std_logic_vector(3 downto 0);
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-- POT
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signal POT_RESET : std_logic;
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signal POT_IN : std_logic_vector(7 downto 0);
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-- scandoubler
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signal half_scandouble_enable_reg : std_logic;
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signal half_scandouble_enable_next : std_logic;
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signal VIDEO_B : std_logic_vector(7 downto 0);
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BEGIN
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-- ANYTHING NOT CONNECTED...
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--GPIO_0(0) <= 'Z';
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--GPIO_0(35 downto 2) <= (others=>'Z');
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--GPIO_1(35 downto 0) <= (others=>'Z');
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FL_OE_N <= '1';
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FL_WE_N <= '1';
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FL_RST_N <= '1';
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FL_ADDR <= (others=>'0');
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LEDG <= (others=>'1');
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LEDR <= (others=>'1');
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-- TODO FUJI? Or Program counter or...
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hexdecoder0 : entity work.hexdecoder
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PORT MAP(CLK => CLK,
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NUMBER => X"5",
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DIGIT => HEX0);
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hexdecoder1 : entity work.hexdecoder
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PORT MAP(CLK => CLK,
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NUMBER => X"2",
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DIGIT => HEX1);
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hexdecoder2 : entity work.hexdecoder
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PORT MAP(CLK => CLK,
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NUMBER => X"0",
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DIGIT => HEX2);
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hexdecoder3 : entity work.hexdecoder
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PORT MAP(CLK => CLK,
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NUMBER => X"0",
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DIGIT => HEX3);
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sram1 : entity work.sram
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PORT MAP(WREN => RAM_WRITE_ENABLE,
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clk => CLK,
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reset_n => RESET_N,
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request => RAM_REQUEST,
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width_16bit => PBI_WIDTH_16BIT_ACCESS,
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ADDRESS => RAM_ADDR,
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DIN => PBI_WRITE_DATA(15 DOWNTO 0),
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SRAM_DQ => SRAM_DQ,
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SRAM_CE_N => SRAM_CE_N,
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SRAM_OE_N => SRAM_OE_N,
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SRAM_WE_N => SRAM_WE_N,
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SRAM_LB_N => SRAM_LB_N,
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SRAM_UB_N => SRAM_UB_N,
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complete => RAM_REQUEST_COMPLETE,
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DOUT => RAM_DO,
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SRAM_ADDR => SRAM_ADDR);
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sdram_adaptor : entity work.sdram_statemachine
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GENERIC MAP(ADDRESS_WIDTH => 22,
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AP_BIT => 10,
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COLUMN_WIDTH => 8,
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ROW_WIDTH => 12
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)
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PORT MAP(CLK_SYSTEM => CLK,
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CLK_SDRAM => CLK_SDRAM,
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RESET_N => RESET_N,
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READ_EN => SDRAM_READ_ENABLE,
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WRITE_EN => SDRAM_WRITE_ENABLE,
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REQUEST => SDRAM_REQUEST,
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BYTE_ACCESS => PBI_WIDTH_8BIT_ACCESS,
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WORD_ACCESS => PBI_WIDTH_16BIT_ACCESS,
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LONGWORD_ACCESS => PBI_WIDTH_32BIT_ACCESS,
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REFRESH => SDRAM_REFRESH,
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ADDRESS_IN => SDRAM_ADDR,
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DATA_IN => PBI_WRITE_DATA(31 downto 0),
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SDRAM_DQ => DRAM_DQ,
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COMPLETE => SDRAM_REQUEST_COMPLETE,
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SDRAM_BA0 => DRAM_BA_0,
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SDRAM_BA1 => DRAM_BA_1,
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SDRAM_CKE => DRAM_CKE,
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SDRAM_CS_N => DRAM_CS_N,
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SDRAM_RAS_N => DRAM_RAS_N,
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SDRAM_CAS_N => DRAM_CAS_N,
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SDRAM_WE_N => DRAM_WE_N,
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SDRAM_ldqm => DRAM_LDQM,
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SDRAM_udqm => DRAM_UDQM,
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DATA_OUT => SDRAM_DO,
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SDRAM_ADDR => DRAM_ADDR(11 downto 0),
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reset_client_n => SDRAM_RESET_N
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);
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-- GTIA triggers
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--GTIA_TRIG <= CART_RD5&"1"&JOY2_n(4)&JOY1_n(4);
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GTIA_TRIG <= TRIGGERS(3 downto 0);
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-- Internal rom/ram
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internalromram1 : entity work.internalromram
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GENERIC MAP
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(
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internal_rom => 0,
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internal_ram => 0
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)
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PORT MAP (
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clock => CLK,
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reset_n => RESET_N,
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ROM_ADDR => ROM_ADDR,
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ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
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ROM_REQUEST => ROM_REQUEST,
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ROM_DATA => ROM_DO,
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RAM_ADDR => RAM_ADDR,
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RAM_WR_ENABLE => RAM_WRITE_ENABLE,
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RAM_DATA_IN => PBI_WRITE_DATA(7 downto 0),
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RAM_REQUEST_COMPLETE => open,
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RAM_REQUEST => RAM_REQUEST,
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RAM_DATA => open
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);
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--sync_switches1 : entity work.sync_switches
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--PORT MAP(CLK => CLK,
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-- KEY => KEY,
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-- SW => SW,
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-- SYNC_KEYS => SYNC_KEYS,
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-- SYNC_SWITCHES => SYNC_SWITCHES);
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gpio0_gen:
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for I in 0 to 35 generate
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gpio_0(I) <= gpio_0_out(I) when gpio_0_dir_out(I)='1' else 'Z';
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end generate gpio0_gen;
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gpio1_gen:
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for I in 0 to 35 generate
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gpio_1(I) <= gpio_1_out(I) when gpio_1_dir_out(I)='1' else 'Z';
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end generate gpio1_gen;
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gpio1 : entity work.gpio
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PORT MAP(clk => CLK,
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gpio_enable => '1',
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pot_reset => pot_reset,
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pbi_write_enable => '0',
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cart_request => '0',
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cart_complete => open,
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cart_data_read => open,
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s4_n => '0',
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s5_n => '0',
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cctl_n => '0',
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cart_data_write => x"00",
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GPIO_0_IN => GPIO_0,
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GPIO_0_OUT => GPIO_0_OUT,
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GPIO_0_DIR_OUT => GPIO_0_DIR_OUT,
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GPIO_1_IN => GPIO_1,
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GPIO_1_OUT => GPIO_1_OUT,
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GPIO_1_DIR_OUT => GPIO_1_DIR_OUT,
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keyboard_scan => KEYBOARD_SCAN, --5200
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pbi_addr_out => X"0000",
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porta_out => (others=>'0'),
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porta_output => (others=>'0'),
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lightpen => open,
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rd4 => open,
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rd5 => open,
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keyboard_response => KEYBOARD_RESPONSE, -- 5200
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porta_in => open,
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pot_in => pot_in,
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trig_in => TRIGGERS, -- 5200
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CA2_DIR_OUT => '0',
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CA2_OUT => '0',
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CA2_IN => open,
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CB2_DIR_OUT => '0',
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CB2_OUT => '0',
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CB2_IN => open,
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SIO_IN => GPIO_SIO_RXD,
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SIO_OUT => SIO_TXD,
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CONSOL => CONSOL_OUT
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);
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process(clk,RESET_N,SDRAM_RESET_N,reset_atari)
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begin
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if ((RESET_N and SDRAM_RESET_N and not(reset_atari))='0') then
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half_scandouble_enable_reg <= '0';
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elsif (clk'event and clk='1') then
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half_scandouble_enable_reg <= half_scandouble_enable_next;
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end if;
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end process;
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half_scandouble_enable_next <= not(half_scandouble_enable_reg);
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scandoubler : entity work.scandoubler
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GENERIC MAP
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(
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video_bits=>4
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)
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PORT MAP(CLK => CLK,
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RESET_N => RESET_N and SDRAM_RESET_N and not(reset_atari),
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VGA => SW(7),
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COMPOSITE_ON_HSYNC => SW(6),
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colour_enable => half_scandouble_enable_reg,
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doubled_enable => '1',
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scanlines_on => SW(5),
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vsync_in => VGA_VS_RAW,
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hsync_in => VGA_HS_RAW,
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csync_in => VGA_CS_RAW,
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pal => '0',
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colour_in => VIDEO_B,
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VSYNC => VGA_VS,
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HSYNC => VGA_HS,
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B => VGA_B,
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G => VGA_G,
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R => VGA_R);
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audio_codec_config_over_i2c : entity work.i2c_loader
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GENERIC MAP(device_address => 26,
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log2_divider => 6,
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num_retries => 0
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)
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PORT MAP(CLK => CLK,
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nRESET => RESET_N,
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I2C_SCL => I2C_SCLK,
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I2C_SDA => I2C_SDAT);
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audio_codec_data : entity work.i2sslave
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PORT MAP(CLK => CLK,
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BCLK => AUD_BCLK,
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DACLRC => AUD_DACLRCK,
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LEFT_IN => AUDIO_LEFT,
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RIGHT_IN => AUDIO_RIGHT,
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MCLK_2 => AUD_XCK,
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DACDAT => AUD_DACDAT);
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|
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pll : entity work.pll
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PORT MAP(inclk0 => CLOCK_50,
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c0 => CLK_SDRAM,
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c1 => CLK,
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c2 => DRAM_CLK,
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locked => PLL_LOCKED);
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--gen_ntsc_pll : if tv=0 generate
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--pll : entity work.pll_ntsc
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--PORT MAP(inclk0 => CLOCK_27(0),
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-- c0 => CLK_SDRAM,
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-- c1 => CLK,
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-- c2 => DRAM_CLK,
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-- locked => PLL_LOCKED);
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--end generate;
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--
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--gen_pal_pll : if tv=1 generate
|
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--pll : entity work.pll_pal
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--PORT MAP(inclk0 => CLOCK_27(0),
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-- c0 => CLK_SDRAM,
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-- c1 => CLK,
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-- c2 => DRAM_CLK,
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-- locked => PLL_LOCKED);
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--end generate;
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RESET_N <= PLL_LOCKED;
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-- PS2 to pokey
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keyboard_map1 : entity work.ps2_to_atari5200
|
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PORT MAP
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(
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CLK => clk,
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RESET_N => reset_n,
|
|
PS2_CLK => ps2_clk,
|
|
PS2_DAT => ps2_dat,
|
|
|
|
KEYBOARD_SCAN => KEYBOARD_SCAN,
|
|
KEYBOARD_RESPONSE => open,
|
|
|
|
FIRE2 => (others=>'0'),
|
|
CONTROLLER_SELECT => (others=>'0'),
|
|
|
|
FKEYS => FKEYS
|
|
);
|
|
|
|
-- SIO
|
|
-- TODO combine
|
|
--SIO_RXD <= UART_RXD;
|
|
UART_TXD <= SIO_TXD;
|
|
--GPIO_0(1) <= SIO_COMMAND;
|
|
|
|
SIO_COMMAND <= 'Z'; -- no PIA...
|
|
zpu_sio_command <= SIO_COMMAND;
|
|
zpu_sio_rxd <= SIO_TXD;
|
|
SIO_RXD <= zpu_sio_txd and UART_RXD;
|
|
|
|
-- VIDEO
|
|
CONSOL_IN <= "1000";
|
|
|
|
atari5200 : entity work.atari5200core
|
|
GENERIC MAP
|
|
(
|
|
cycle_length => 32,
|
|
video_bits => 8,
|
|
palette => 0
|
|
)
|
|
PORT MAP
|
|
(
|
|
CLK => CLK,
|
|
RESET_N => RESET_N and SDRAM_RESET_N and not(reset_atari),
|
|
|
|
VIDEO_VS => VGA_VS_RAW,
|
|
VIDEO_HS => VGA_HS_RAW,
|
|
VIDEO_CS => VGA_CS_RAW,
|
|
VIDEO_B => VIDEO_B,
|
|
VIDEO_G => open,
|
|
VIDEO_R => open,
|
|
|
|
AUDIO_L => AUDIO_LEFT,
|
|
AUDIO_R => AUDIO_RIGHT,
|
|
|
|
KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
|
|
KEYBOARD_SCAN => KEYBOARD_SCAN,
|
|
|
|
POT_IN => POT_IN,
|
|
POT_RESET => POT_RESET,
|
|
|
|
PBI_ADDR => open,
|
|
PBI_WRITE_ENABLE => open,
|
|
PBI_SNOOP_DATA => open,
|
|
PBI_WRITE_DATA => PBI_WRITE_DATA,
|
|
PBI_WIDTH_8bit_ACCESS => PBI_WIDTH_8bit_ACCESS,
|
|
PBI_WIDTH_16bit_ACCESS => PBI_WIDTH_16bit_ACCESS,
|
|
PBI_WIDTH_32bit_ACCESS => PBI_WIDTH_32bit_ACCESS,
|
|
|
|
PBI_ROM_DO => "11111111",
|
|
PBI_REQUEST => open,
|
|
PBI_REQUEST_COMPLETE => '1',
|
|
|
|
SIO_RXD => SIO_RXD,
|
|
SIO_TXD => SIO_TXD,
|
|
|
|
CONSOL_OUT => CONSOL_OUT,
|
|
CONSOL_IN => CONSOL_IN,
|
|
GTIA_TRIG => GTIA_TRIG,
|
|
|
|
SDRAM_REQUEST => SDRAM_REQUEST,
|
|
SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
|
|
SDRAM_READ_ENABLE => SDRAM_READ_ENABLE,
|
|
SDRAM_WRITE_ENABLE => SDRAM_WRITE_ENABLE,
|
|
SDRAM_ADDR => SDRAM_ADDR,
|
|
SDRAM_DO => SDRAM_DO,
|
|
|
|
ANTIC_REFRESH => SDRAM_REFRESH,
|
|
|
|
RAM_ADDR => RAM_ADDR,
|
|
RAM_DO => RAM_DO,
|
|
RAM_REQUEST => RAM_REQUEST,
|
|
RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,
|
|
RAM_WRITE_ENABLE => RAM_WRITE_ENABLE,
|
|
|
|
ROM_ADDR => ROM_ADDR,
|
|
ROM_DO => ROM_DO,
|
|
ROM_REQUEST => ROM_REQUEST,
|
|
ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
|
|
|
|
DMA_FETCH => dma_fetch,
|
|
DMA_READ_ENABLE => dma_read_enable,
|
|
DMA_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
|
|
DMA_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
|
|
DMA_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
|
|
DMA_ADDR => dma_addr_fetch,
|
|
DMA_WRITE_DATA => dma_write_data,
|
|
MEMORY_READY_DMA => dma_memory_ready,
|
|
--DMA_MEMORY_DATA => dma_memory_data,
|
|
PBI_SNOOP_DATA => DMA_MEMORY_DATA,
|
|
|
|
USE_SDRAM => '1', --SW(9), -- TODO
|
|
ROM_IN_RAM => '1',
|
|
HALT => pause_atari,
|
|
THROTTLE_COUNT_6502 => speed_6502
|
|
);
|
|
|
|
zpu: entity work.zpucore
|
|
GENERIC MAP
|
|
(
|
|
platform => 1,
|
|
spi_clock_div => 1 -- 28MHz/2. Max for SD cards is 25MHz...
|
|
)
|
|
PORT MAP
|
|
(
|
|
-- standard...
|
|
CLK => CLK,
|
|
RESET_N => RESET_N and sdram_reset_n,
|
|
|
|
-- dma bus master (with many waitstates...)
|
|
ZPU_ADDR_FETCH => dma_addr_fetch,
|
|
ZPU_DATA_OUT => dma_write_data,
|
|
ZPU_FETCH => dma_fetch,
|
|
ZPU_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
|
|
ZPU_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
|
|
ZPU_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
|
|
ZPU_READ_ENABLE => dma_read_enable,
|
|
ZPU_MEMORY_READY => dma_memory_ready,
|
|
ZPU_MEMORY_DATA => dma_memory_data,
|
|
|
|
-- rom bus master
|
|
-- data on next cycle after addr
|
|
ZPU_ADDR_ROM => zpu_addr_rom,
|
|
ZPU_ROM_DATA => zpu_rom_data,
|
|
|
|
-- spi master
|
|
-- Too painful to bit bang spi from zpu, so we have a hardware master in here
|
|
ZPU_SD_DAT0 => sd_data,
|
|
ZPU_SD_CLK => sd_clk,
|
|
ZPU_SD_CMD => sd_cmd,
|
|
ZPU_SD_DAT3 => sd_three,
|
|
|
|
-- SIO
|
|
-- Ditto for speaking to Atari, we have a built in Pokey
|
|
ZPU_POKEY_ENABLE => zpu_pokey_enable,
|
|
ZPU_SIO_TXD => zpu_sio_txd,
|
|
ZPU_SIO_RXD => zpu_sio_rxd,
|
|
ZPU_SIO_COMMAND => zpu_sio_command,
|
|
|
|
-- external control
|
|
-- switches etc. sector DMA blah blah.
|
|
ZPU_IN1 => X"00000"&FKEYS,
|
|
ZPU_IN2 => X"00000000",
|
|
ZPU_IN3 => X"00000000",
|
|
ZPU_IN4 => X"00000000",
|
|
|
|
-- ouputs - e.g. Atari system control, halt, throttle, rom select
|
|
ZPU_OUT1 => zpu_out1,
|
|
ZPU_OUT2 => zpu_out2,
|
|
ZPU_OUT3 => zpu_out3,
|
|
ZPU_OUT4 => zpu_out4
|
|
);
|
|
|
|
pause_atari <= zpu_out1(0);
|
|
reset_atari <= zpu_out1(1);
|
|
speed_6502 <= zpu_out1(7 downto 2);
|
|
|
|
zpu_rom1: entity work.zpu_rom
|
|
port map(
|
|
clock => clk,
|
|
address => zpu_addr_rom(13 downto 2),
|
|
q => zpu_rom_data
|
|
);
|
|
|
|
enable_179_clock_div_zpu_pokey : entity work.enable_divider
|
|
generic map (COUNT=>32) -- cycle_length
|
|
port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>zpu_pokey_enable);
|
|
|
|
END vhdl;
|