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module usbDeviceXilinxTop (
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//
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// Global signals
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//
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clk,
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//
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// misc Starter Kit control sigs
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//
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E_NRST,
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SPI_SCK,
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NF_CE,
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SD_CS,
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//
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// USB slave
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//
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usbSlaveVP,
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usbSlaveVM,
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usbSlaveOE_n,
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usbDPlusPullup
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);
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//
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// Global signals
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//
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input clk;
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//
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// misc Starter Kit control sigs
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//
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output E_NRST;
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output SPI_SCK;
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output NF_CE;
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output SD_CS;
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//
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// USB slave
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//
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inout usbSlaveVP;
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inout usbSlaveVM;
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output usbSlaveOE_n;
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output usbDPlusPullup;
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//local wires and regs
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reg [1:0] rstReg;
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wire rst;
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wire pll_locked;
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wire clk48MHz;
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assign E_NRST = 1'b0;
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assign SPI_SCK = 1'b0;
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assign NF_CE = 1'b0;
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assign SD_CS = 1'b1;
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pll_48MHz_xilinx pll_48MHz_inst (
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.CLKIN_IN ( clk ),
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.CLK0_OUT (clk48MHz),
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.LOCKED_OUT( pll_locked)
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);
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//generate sync reset from pll lock signal
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always @(posedge clk48MHz) begin
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rstReg[1:0] <= {rstReg[0], ~pll_locked};
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end
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assign rst = rstReg[1];
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usbDevice u_usbDevice (
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.clk(clk48MHz),
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.rst(rst),
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.usbSlaveVP_in(usbSlaveVP_in),
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.usbSlaveVM_in(usbSlaveVM_in),
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.usbSlaveVP_out(usbSlaveVP_out),
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.usbSlaveVM_out(usbSlaveVM_out),
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.usbSlaveOE_n(usbSlaveOE_n),
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.usbDPlusPullup(usbDPlusPullup),
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.vBusDetect(1'b1)
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);
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assign {usbSlaveVP_in, usbSlaveVM_in} = {usbSlaveVP, usbSlaveVM};
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assign {usbSlaveVP, usbSlaveVM} = (usbSlaveOE_n == 1'b0) ? {usbSlaveVP_out, usbSlaveVM_out} : 2'bzz;
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endmodule
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