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`include "timescale.v"
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module testHarness( );
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// -----------------------------------
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// Local Wires
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// -----------------------------------
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reg clk;
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reg rst;
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reg usbClk;
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wire [8:0] adr;
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wire [7:0] masterDout;
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wire [7:0] masterDin;
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wire [7:0] usbSlaveDout;
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wire [7:0] usbHostDout;
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wire stb;
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wire we;
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wire ack;
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wire host_stb;
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wire slave_stb;
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wire DPlusPullup;
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wire DPlusPullDown;
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wire DMinusPullup;
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wire DMinusPulDown;
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reg USBWireVP;
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reg USBWireVM;
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wire [1:0] hostUSBWireDataIn;
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wire [1:0] hostUSBWireDataOut;
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wire [1:0] slaveUSBWireDataIn;
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wire [1:0] slaveUSBWireDataOut;
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wire hostUSBWireCtrlOut;
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wire slaveUSBWireCtrlOut;
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initial begin
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$dumpfile("wave.vcd");
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$dumpvars(0, testHarness);
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end
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pullup(DPlusPullup);
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pulldown(DPlusPullDown);
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pullup(DMinusPullup);
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pulldown(DMinusPullDown);
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assign hostUSBWireDataIn = {USBWireVP, USBWireVM};
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assign slaveUSBWireDataIn = {USBWireVP, USBWireVM};
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//always @(hostUSBWireCtrlOut or slaveUSBWireCtrlOut or hostUSBWireDataOut or slaveUSBWireDataOut or
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// DPlusPullup or DPlusPullDown or DMinusPullup or DMinusPullDown) begin
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always @(*) begin
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if (hostUSBWireCtrlOut == 1'b1 && slaveUSBWireCtrlOut == 1'b0)
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{USBWireVP, USBWireVM} <= hostUSBWireDataOut;
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else if (hostUSBWireCtrlOut == 1'b0 && slaveUSBWireCtrlOut == 1'b1)
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{USBWireVP, USBWireVM} <= slaveUSBWireDataOut;
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else if (hostUSBWireCtrlOut == 1'b1 && slaveUSBWireCtrlOut == 1'b1)
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{USBWireVP, USBWireVM} <= 2'bxx;
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else if (hostUSBWireCtrlOut == 1'b0 && slaveUSBWireCtrlOut == 1'b0) begin
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if (USBDPlusPullup == 1'b1)
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USBWireVP <= DPlusPullup;
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else
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USBWireVP <= DPlusPullDown;
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if (USBDMinusPullup == 1'b1)
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USBWireVM <= DMinusPullup;
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else
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USBWireVM <= DMinusPullDown;
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end
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end
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assign host_stb = ~adr[8] & stb;
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assign slave_stb = adr[8] & stb;
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assign masterDin = host_stb == 1'b1 ? usbHostDout : usbSlaveDout;
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//Parameters declaration:
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defparam u_usbHost.HOST_FIFO_DEPTH = 64;
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parameter HOST_FIFO_DEPTH = 64;
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defparam u_usbHost.HOST_FIFO_ADDR_WIDTH = 6;
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parameter HOST_FIFO_ADDR_WIDTH = 6;
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usbHost u_usbHost (
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.clk_i(clk),
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.rst_i(rst),
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.address_i(adr[7:0]),
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.data_i(masterDout),
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.data_o(usbHostDout),
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.we_i(we),
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.strobe_i(host_stb),
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.ack_o(ack),
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.usbClk(usbClk),
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.hostSOFSentIntOut(hostSOFSentIntOut),
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.hostConnEventIntOut(hostConnEventIntOut),
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.hostResumeIntOut(hostResumeIntOut),
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.hostTransDoneIntOut(hostTransDoneIntOut),
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.USBWireDataIn(hostUSBWireDataIn),
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.USBWireDataInTick(USBWireDataInTick),
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.USBWireDataOut(hostUSBWireDataOut),
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.USBWireDataOutTick(USBWireDataOutTick),
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.USBWireCtrlOut(hostUSBWireCtrlOut),
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.USBFullSpeed(USBFullSpeed)
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);
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//Parameters declaration:
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defparam u_usbSlave.EP0_FIFO_DEPTH = 64;
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parameter EP0_FIFO_DEPTH = 64;
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defparam u_usbSlave.EP0_FIFO_ADDR_WIDTH = 6;
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parameter EP0_FIFO_ADDR_WIDTH = 6;
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defparam u_usbSlave.EP1_FIFO_DEPTH = 64;
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parameter EP1_FIFO_DEPTH = 64;
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defparam u_usbSlave.EP1_FIFO_ADDR_WIDTH = 6;
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parameter EP1_FIFO_ADDR_WIDTH = 6;
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defparam u_usbSlave.EP2_FIFO_DEPTH = 64;
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parameter EP2_FIFO_DEPTH = 64;
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defparam u_usbSlave.EP2_FIFO_ADDR_WIDTH = 6;
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parameter EP2_FIFO_ADDR_WIDTH = 6;
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defparam u_usbSlave.EP3_FIFO_DEPTH = 64;
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parameter EP3_FIFO_DEPTH = 64;
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defparam u_usbSlave.EP3_FIFO_ADDR_WIDTH = 6;
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parameter EP3_FIFO_ADDR_WIDTH = 6;
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usbSlave u_usbSlave (
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.clk_i(clk),
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.rst_i(rst),
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.address_i(adr[7:0]),
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.data_i(masterDout),
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.data_o(usbSlaveDout),
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.we_i(we),
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.strobe_i(slave_stb),
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.ack_o(ack),
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.usbClk(usbClk),
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.slaveSOFRxedIntOut(slaveSOFRxedIntOut),
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.slaveResetEventIntOut(slaveResetEventIntOut),
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.slaveResumeIntOut(slaveResumeIntOut),
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.slaveTransDoneIntOut(slaveTransDoneIntOut),
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.slaveNAKSentIntOut(slaveNAKSentIntOut),
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.slaveVBusDetIntOut(slaveVBusDetIntOut),
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.USBWireDataIn(slaveUSBWireDataIn),
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.USBWireDataInTick(USBWireDataInTick),
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.USBWireDataOut(slaveUSBWireDataOut),
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.USBWireDataOutTick(USBWireDataOutTick),
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.USBWireCtrlOut(slaveUSBWireCtrlOut),
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.USBFullSpeed(USBFullSpeed),
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.USBDPlusPullup(USBDPlusPullup),
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.USBDMinusPullup(USBDMinusPullup),
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.vBusDetect(1'b1)
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);
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wb_master_model #(.dwidth(8), .awidth(9)) u_wb_master_model (
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.clk(clk),
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.rst(rst),
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.adr(adr),
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.din(masterDin),
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.dout(masterDout),
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.cyc(),
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.stb(stb),
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.we(we),
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.sel(),
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.ack(ack),
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.err(1'b0),
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.rty(1'b0)
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);
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//--------------- reset ---------------
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initial begin
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@(posedge clk);
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@(posedge clk);
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@(posedge clk);
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@(posedge clk);
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@(posedge clk);
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@(posedge clk);
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@(posedge clk);
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@(posedge clk);
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rst <= 1'b1;
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@(posedge clk);
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rst <= 1'b0;
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@(posedge clk);
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end
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// ****************************** Clock section ******************************
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`define CLK_50MHZ_HALF_PERIOD 10
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`define CLK_25MHZ_HALF_PERIOD 20
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always begin
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#`CLK_25MHZ_HALF_PERIOD clk <= 1'b0;
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#`CLK_25MHZ_HALF_PERIOD clk <= 1'b1;
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end
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always begin
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#`CLK_50MHZ_HALF_PERIOD usbClk <= 1'b0;
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#`CLK_50MHZ_HALF_PERIOD usbClk <= 1'b1;
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end
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endmodule
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