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//////////////////////////////////////////////////////////////////////
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//// ////
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//// hostController
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// http://www.opencores.org/cores/usbhostslave/ ////
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//// ////
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//// Module Description: ////
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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`include "usbHostControl_h.v"
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`include "usbConstants_h.v"
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module hostcontroller (RXStatus, clearTXReq, clk, getPacketREn, getPacketRdy, isoEn, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);
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input [7:0] RXStatus;
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input clk;
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input getPacketRdy;
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input isoEn;
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input rst;
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input sendPacketArbiterGnt;
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input sendPacketRdy;
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input transReq;
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input [1:0] transType;
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output clearTXReq;
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output getPacketREn;
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output sendPacketArbiterReq;
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output [3:0] sendPacketPID;
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output sendPacketWEn;
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output transDone;
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wire [7:0] RXStatus;
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reg clearTXReq, next_clearTXReq;
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wire clk;
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reg getPacketREn, next_getPacketREn;
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wire getPacketRdy;
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wire isoEn;
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wire rst;
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wire sendPacketArbiterGnt;
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reg sendPacketArbiterReq, next_sendPacketArbiterReq;
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reg [3:0] sendPacketPID, next_sendPacketPID;
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wire sendPacketRdy;
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reg sendPacketWEn, next_sendPacketWEn;
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reg transDone, next_transDone;
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wire transReq;
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wire [1:0] transType;
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// diagram signals declarations
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reg [3:0]delCnt, next_delCnt;
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// BINARY ENCODED state machine: hstCntrl
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// State codes definitions:
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`define START_HC 6'b000000
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`define TX_REQ 6'b000001
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`define CHK_TYPE 6'b000010
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`define FLAG 6'b000011
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`define IN_WAIT_DATA_RXED 6'b000100
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`define IN_CHK_FOR_ERROR 6'b000101
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`define IN_CLR_SP_WEN2 6'b000110
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`define SETUP_CLR_SP_WEN1 6'b000111
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`define SETUP_CLR_SP_WEN2 6'b001000
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`define FIN 6'b001001
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`define WAIT_GNT 6'b001010
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`define SETUP_WAIT_PKT_RXED 6'b001011
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`define IN_WAIT_IN_SENT 6'b001100
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`define OUT0_WAIT_RX_DATA 6'b001101
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`define OUT0_WAIT_DATA0_SENT 6'b001110
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`define OUT0_WAIT_OUT_SENT 6'b001111
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`define SETUP_HC_WAIT_RDY 6'b010000
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`define IN_WAIT_SP_RDY1 6'b010001
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`define IN_WAIT_SP_RDY2 6'b010010
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`define OUT0_WAIT_SP_RDY1 6'b010011
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`define SETUP_WAIT_SETUP_SENT 6'b010100
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`define SETUP_WAIT_DATA_SENT 6'b010101
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`define IN_CLR_SP_WEN1 6'b010110
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`define IN_WAIT_ACK_SENT 6'b010111
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`define OUT0_CLR_WEN1 6'b011000
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`define OUT0_CLR_WEN2 6'b011001
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`define OUT1_WAIT_RX_DATA 6'b011010
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`define OUT1_WAIT_OUT_SENT 6'b011011
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`define OUT1_WAIT_DATA1_SENT 6'b011100
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`define OUT1_WAIT_SP_RDY1 6'b011101
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`define OUT1_CLR_WEN1 6'b011110
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`define OUT1_CLR_WEN2 6'b011111
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`define OUT0_CHK_ISO 6'b100000
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reg [5:0] CurrState_hstCntrl;
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reg [5:0] NextState_hstCntrl;
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//--------------------------------------------------------------------
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// Machine: hstCntrl
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//--------------------------------------------------------------------
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//----------------------------------
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// Next State Logic (combinatorial)
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//----------------------------------
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always @ (delCnt or transReq or transType or sendPacketArbiterGnt or getPacketRdy or sendPacketRdy or isoEn or RXStatus or sendPacketArbiterReq or transDone or clearTXReq or sendPacketWEn or getPacketREn or sendPacketPID or CurrState_hstCntrl)
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begin : hstCntrl_NextState
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NextState_hstCntrl <= CurrState_hstCntrl;
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// Set default values for outputs and signals
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next_sendPacketArbiterReq <= sendPacketArbiterReq;
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next_transDone <= transDone;
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next_clearTXReq <= clearTXReq;
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next_delCnt <= delCnt;
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next_sendPacketWEn <= sendPacketWEn;
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next_getPacketREn <= getPacketREn;
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next_sendPacketPID <= sendPacketPID;
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case (CurrState_hstCntrl) // synopsys parallel_case full_case
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`START_HC:
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NextState_hstCntrl <= `TX_REQ;
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`TX_REQ:
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if (transReq == 1'b1)
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begin
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NextState_hstCntrl <= `WAIT_GNT;
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next_sendPacketArbiterReq <= 1'b1;
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end
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`CHK_TYPE:
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if (transType == `IN_TRANS)
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NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
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else if (transType == `OUTDATA0_TRANS)
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NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
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else if (transType == `OUTDATA1_TRANS)
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NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
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else if (transType == `SETUP_TRANS)
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NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
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`FLAG:
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begin
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next_transDone <= 1'b1;
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next_clearTXReq <= 1'b1;
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next_sendPacketArbiterReq <= 1'b0;
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next_delCnt <= 4'h0;
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NextState_hstCntrl <= `FIN;
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end
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`FIN:
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begin
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next_clearTXReq <= 1'b0;
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next_transDone <= 1'b0;
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next_delCnt <= delCnt + 1'b1;
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//now wait for 'transReq' to clear
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if (delCnt == 4'hf)
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NextState_hstCntrl <= `TX_REQ;
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end
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`WAIT_GNT:
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if (sendPacketArbiterGnt == 1'b1)
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NextState_hstCntrl <= `CHK_TYPE;
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`SETUP_CLR_SP_WEN1:
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begin
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next_sendPacketWEn <= 1'b0;
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NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
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end
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`SETUP_CLR_SP_WEN2:
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begin
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next_sendPacketWEn <= 1'b0;
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NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
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end
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`SETUP_WAIT_PKT_RXED:
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begin
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next_getPacketREn <= 1'b0;
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if (getPacketRdy == 1'b1)
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NextState_hstCntrl <= `FLAG;
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end
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`SETUP_HC_WAIT_RDY:
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if (sendPacketRdy == 1'b1)
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begin
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NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
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next_sendPacketWEn <= 1'b1;
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next_sendPacketPID <= `SETUP;
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end
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`SETUP_WAIT_SETUP_SENT:
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if (sendPacketRdy == 1'b1)
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begin
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NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
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next_sendPacketWEn <= 1'b1;
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next_sendPacketPID <= `DATA0;
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end
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`SETUP_WAIT_DATA_SENT:
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if (sendPacketRdy == 1'b1)
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begin
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NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
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next_getPacketREn <= 1'b1;
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end
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`IN_WAIT_DATA_RXED:
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begin
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next_getPacketREn <= 1'b0;
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if (getPacketRdy == 1'b1)
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NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
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end
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`IN_CHK_FOR_ERROR:
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if (isoEn == 1'b1)
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NextState_hstCntrl <= `FLAG;
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else if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
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RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
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RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
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RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
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RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
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RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
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NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
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else
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NextState_hstCntrl <= `FLAG;
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`IN_CLR_SP_WEN2:
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begin
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next_sendPacketWEn <= 1'b0;
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NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
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end
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`IN_WAIT_IN_SENT:
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if (sendPacketRdy == 1'b1)
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begin
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NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
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next_getPacketREn <= 1'b1;
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end
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`IN_WAIT_SP_RDY1:
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if (sendPacketRdy == 1'b1)
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begin
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NextState_hstCntrl <= `IN_CLR_SP_WEN1;
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next_sendPacketWEn <= 1'b1;
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next_sendPacketPID <= `IN;
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end
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`IN_WAIT_SP_RDY2:
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if (sendPacketRdy == 1'b1)
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begin
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NextState_hstCntrl <= `IN_CLR_SP_WEN2;
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next_sendPacketWEn <= 1'b1;
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next_sendPacketPID <= `ACK;
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end
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`IN_CLR_SP_WEN1:
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begin
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next_sendPacketWEn <= 1'b0;
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NextState_hstCntrl <= `IN_WAIT_IN_SENT;
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end
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`IN_WAIT_ACK_SENT:
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if (sendPacketRdy == 1'b1)
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NextState_hstCntrl <= `FLAG;
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`OUT0_WAIT_RX_DATA:
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begin
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next_getPacketREn <= 1'b0;
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if (getPacketRdy == 1'b1)
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NextState_hstCntrl <= `FLAG;
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end
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`OUT0_WAIT_DATA0_SENT:
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if (sendPacketRdy == 1'b1)
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NextState_hstCntrl <= `OUT0_CHK_ISO;
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`OUT0_WAIT_OUT_SENT:
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if (sendPacketRdy == 1'b1)
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begin
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NextState_hstCntrl <= `OUT0_CLR_WEN2;
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next_sendPacketWEn <= 1'b1;
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next_sendPacketPID <= `DATA0;
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end
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`OUT0_WAIT_SP_RDY1:
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if (sendPacketRdy == 1'b1)
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begin
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NextState_hstCntrl <= `OUT0_CLR_WEN1;
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next_sendPacketWEn <= 1'b1;
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next_sendPacketPID <= `OUT;
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end
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`OUT0_CLR_WEN1:
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begin
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next_sendPacketWEn <= 1'b0;
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NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
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end
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`OUT0_CLR_WEN2:
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begin
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next_sendPacketWEn <= 1'b0;
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NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
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end
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`OUT0_CHK_ISO:
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if (isoEn == 1'b0)
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begin
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NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
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next_getPacketREn <= 1'b1;
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end
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else
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NextState_hstCntrl <= `FLAG;
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`OUT1_WAIT_RX_DATA:
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begin
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next_getPacketREn <= 1'b0;
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if (getPacketRdy == 1'b1)
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NextState_hstCntrl <= `FLAG;
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end
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`OUT1_WAIT_OUT_SENT:
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if (sendPacketRdy == 1'b1)
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begin
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NextState_hstCntrl <= `OUT1_CLR_WEN2;
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next_sendPacketWEn <= 1'b1;
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next_sendPacketPID <= `DATA1;
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end
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`OUT1_WAIT_DATA1_SENT:
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if (sendPacketRdy == 1'b1)
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begin
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NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
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next_getPacketREn <= 1'b1;
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end
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`OUT1_WAIT_SP_RDY1:
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if (sendPacketRdy == 1'b1)
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begin
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NextState_hstCntrl <= `OUT1_CLR_WEN1;
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next_sendPacketWEn <= 1'b1;
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next_sendPacketPID <= `OUT;
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end
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`OUT1_CLR_WEN1:
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begin
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next_sendPacketWEn <= 1'b0;
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NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
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end
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`OUT1_CLR_WEN2:
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begin
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next_sendPacketWEn <= 1'b0;
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NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
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end
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endcase
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end
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//----------------------------------
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// Current State Logic (sequential)
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//----------------------------------
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always @ (posedge clk)
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begin : hstCntrl_CurrentState
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if (rst)
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CurrState_hstCntrl <= `START_HC;
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else
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CurrState_hstCntrl <= NextState_hstCntrl;
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end
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//----------------------------------
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// Registered outputs logic
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//----------------------------------
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always @ (posedge clk)
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begin : hstCntrl_RegOutput
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if (rst)
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begin
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delCnt <= 4'h0;
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transDone <= 1'b0;
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clearTXReq <= 1'b0;
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getPacketREn <= 1'b0;
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sendPacketArbiterReq <= 1'b0;
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sendPacketWEn <= 1'b0;
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sendPacketPID <= 4'b0;
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end
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else
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begin
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delCnt <= next_delCnt;
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transDone <= next_transDone;
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clearTXReq <= next_clearTXReq;
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getPacketREn <= next_getPacketREn;
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sendPacketArbiterReq <= next_sendPacketArbiterReq;
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sendPacketWEn <= next_sendPacketWEn;
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sendPacketPID <= next_sendPacketPID;
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end
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end
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endmodule
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