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---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_MISC.all;
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use ieee.numeric_std.all;
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LIBRARY work;
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-- There is a higher level that just wires up internal ROM/RAM/joysticks to demonstrate how to use this
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-- Also see board specific top levels
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ENTITY atari5200core IS
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GENERIC
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(
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cycle_length : integer := 16; -- or 32...
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video_bits : integer := 8;
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palette : integer :=0; -- 0:gtia colour on VIDEO_B, 1:on
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low_memory : integer := 0; -- 0:8MB memory map, 1:1MB memory map
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internal_ram : integer := 0
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);
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PORT
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(
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CLK : IN STD_LOGIC; -- cycle_length*1.79MHz
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RESET_N : IN STD_LOGIC;
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-- VIDEO OUT - NTSC, original Atari timings approx (may be higher res)
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VIDEO_VS : OUT STD_LOGIC;
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VIDEO_HS : OUT STD_LOGIC;
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VIDEO_CS : OUT STD_LOGIC;
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VIDEO_B : OUT STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);
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VIDEO_G : OUT STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);
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VIDEO_R : OUT STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);
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VIDEO_BLANK : out std_logic;
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VIDEO_BURST : out std_logic;
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VIDEO_START_OF_FIELD : out std_logic;
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VIDEO_ODD_LINE : out std_logic;
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-- AUDIO OUT - Pokey/GTIA 1-bit and Covox all mixed
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-- TODO - choose stereo/mono pokey
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AUDIO_L : OUT std_logic_vector(15 downto 0);
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AUDIO_R : OUT std_logic_vector(15 downto 0);
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-- Pokey keyboard matrix
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-- Standard component available to connect this to PS2
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KEYBOARD_RESPONSE : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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KEYBOARD_SCAN : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
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-- Pokey pots
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POT_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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POT_RESET : OUT STD_LOGIC;
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-- PBI
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PBI_ADDR : out STD_LOGIC_VECTOR(15 DOWNTO 0);
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PBI_WRITE_ENABLE : out STD_LOGIC; -- currently only for CART config...
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PBI_SNOOP_DATA : out std_logic_vector(31 downto 0); -- snoop the bus (i.e. what gets feed to the CPU data in)
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PBI_WRITE_DATA : out std_logic_vector(31 downto 0); -- we want to write this to external ram
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PBI_WIDTH_8bit_ACCESS : out std_logic;
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PBI_WIDTH_16bit_ACCESS : out std_logic;
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PBI_WIDTH_32bit_ACCESS : out std_logic;
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-- TODO - review this mechanism
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-- Since this is intended for real carts, instead should use real timing, though perhaps that can be external...
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PBI_ROM_DO : in STD_LOGIC_VECTOR(7 DOWNTO 0);
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PBI_REQUEST : out STD_LOGIC;
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PBI_REQUEST_COMPLETE : in STD_LOGIC;
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-- TODO - also need to allow rest of PBI accesses, refresh handling etc. Can wait...
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-- TODO MPD, IRQ, RDY, REFRESH, EXTSEL, RST
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-- CARTRIDGE ACCESS (need this, but need to review how it works...)
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-- (R/W/DO on PBI)
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--CART_RD4 : in STD_LOGIC;
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--CART_RD5 : in STD_LOGIC;
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--CART_S4_n : out STD_LOGIC;
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--CART_S5_N : out STD_LOGIC;
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--CART_CCTL_N : out std_logic;
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-- SIO
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SIO_RXD : in std_logic;
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SIO_TXD : out std_logic;
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-- SIO_COMMAND_TX - see PIA PB2
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-- TODO CLOCK IN/CLOCK OUT (unused almost everywhere...)
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-- GTIA consol
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CONSOL_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
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CONSOL_IN : IN STD_LOGIC_VECTOR(3 downto 0);
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GTIA_TRIG : IN STD_LOGIC_VECTOR(3 downto 0);
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-- ANTIC lightpen
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ANTIC_REFRESH : out STD_LOGIC; -- 1 'original' cycle high when antic doing refresh cycle...
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-----------------------
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-- After here all FPGA implementation specific
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-- e.g. need to write up RAM/ROM
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-- we can dma from memory space
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-- etc.
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-- External RAM/ROM - adhere to standard memory map
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-- TODO - lower/upper memory split defined by generic
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-- (TODO SRAM lower ram, SDRAM upper ram - no overlap?)
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---- SRAM memory map (512k) (if USE_SDRAM=0)
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---- base 64k RAM - banks 0-3 "000 0000 1111 1111 1111 1111" (TOP)
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---- to 512k RAM - banks 4-31 "000 0111 1111 1111 1111 1111" (TOP)
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---- SDRAM memory map (8MB) (lower 512k if USE_SDRAM=1)
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---- base 64k RAM - banks 0-3 "000 0000 1111 1111 1111 1111" (TOP)
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---- to 512k RAM - banks 4-31 "000 0111 1111 1111 1111 1111" (TOP)
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---- to 4MB RAM - banks 32-255 "011 1111 1111 1111 1111 1111" (TOP)
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---- +64k - banks 256-259"100 0000 0000 1111 1111 1111" (TOP)
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---- SCRATCH - 4MB+64k-5MB
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---- CARTS - "101 YYYY YYY0 0000 0000 0000" (BOT) - 2MB! 8kb banks
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--SDRAM_CART_ADDR <= "101"&cart_select& "0000000000000";
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---- BASIC/OS ROM - "111 XXXX XX00 0000 0000 0000" (BOT) (BASIC IN SLOT 0!), 2nd to last 512K
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--SDRAM_BASIC_ROM_ADDR <= "111"&"000000" &"00000000000000";
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--SDRAM_OS_ROM_ADDR <= "111"&rom_select &"00000000000000";
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---- SYSTEM - "111 1000 0000 0000 0000 0000" (BOT) - LAST 512K
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-- TODO - review if we need to pass out so many of these
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-- Perhaps we can simplify address decoder and have an external layer?
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SDRAM_REQUEST : OUT std_logic;
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SDRAM_REQUEST_COMPLETE : IN std_logic;
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SDRAM_READ_ENABLE : out STD_LOGIC;
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SDRAM_WRITE_ENABLE : out std_logic;
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SDRAM_ADDR : out STD_LOGIC_VECTOR(22 DOWNTO 0);
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SDRAM_DO : in STD_LOGIC_VECTOR(31 DOWNTO 0);
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RAM_ADDR : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
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RAM_DO : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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RAM_REQUEST : OUT STD_LOGIC;
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RAM_REQUEST_COMPLETE : IN STD_LOGIC;
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RAM_WRITE_ENABLE : OUT STD_LOGIC;
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ROM_ADDR : OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
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ROM_DO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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ROM_REQUEST : OUT STD_LOGIC;
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ROM_REQUEST_COMPLETE : IN STD_LOGIC;
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ROM_WRITE_ENABLE : OUT STD_LOGIC;
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-- DMA memory map differs
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-- e.g. some special addresses to read behind hardware registers
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-- 0x0000-0xffff: Atari registers + 3 mirrors (bit 16/17)
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-- 23 downto 21:
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-- 001 : SRAM,512k
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-- 010|011 : ROM, 4MB
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-- 10xx : SDRAM, 8MB (If you have more, its unmapped for now... Can bank switch! Atari can't access this much anyway...)
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DMA_FETCH : in STD_LOGIC; -- we want to read/write
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DMA_READ_ENABLE : in std_logic;
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DMA_32BIT_WRITE_ENABLE : in std_logic;
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DMA_16BIT_WRITE_ENABLE : in std_logic;
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DMA_8BIT_WRITE_ENABLE : in std_logic;
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DMA_ADDR : in std_logic_vector(23 downto 0);
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DMA_WRITE_DATA : in std_logic_vector(31 downto 0);
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MEMORY_READY_DMA : out std_logic; -- op complete
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-- Special config params
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ROM_IN_RAM : in std_logic;
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HALT : in std_logic;
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THROTTLE_COUNT_6502 : in STD_LOGIC_VECTOR(5 DOWNTO 0)
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);
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END atari5200core;
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ARCHITECTURE bdf_type OF atari5200core IS
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-- ANTIC
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SIGNAL ANTIC_ADDR : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL ANTIC_AN : STD_LOGIC_VECTOR(2 DOWNTO 0);
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SIGNAL ANTIC_COLOUR_CLOCK_OUT : STD_LOGIC;
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SIGNAL ANTIC_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL CACHE_ANTIC_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL ANTIC_FETCH : STD_LOGIC;
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SIGNAL ANTIC_HIGHRES_COLOUR_CLOCK_OUT : STD_LOGIC;
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SIGNAL ANTIC_ORIGINAL_COLOUR_CLOCK_OUT : STD_LOGIC;
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SIGNAL ANTIC_RDY : STD_LOGIC;
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SIGNAL ANTIC_WRITE_ENABLE : STD_LOGIC;
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signal hcount_temp : std_logic_vector(7 downto 0);
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signal vcount_temp : std_logic_vector(8 downto 0);
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signal ANTIC_REFRESH_CYCLE : STD_LOGIC;
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-- GTIA
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SIGNAL GTIA_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL CACHE_GTIA_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL GTIA_WRITE_ENABLE : STD_LOGIC;
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signal COLOUR : std_logic_vector(7 downto 0);
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-- GTIA PALETTE
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signal VIDEO_R_WIDE : std_logic_vector(7 downto 0);
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signal VIDEO_G_WIDE : std_logic_vector(7 downto 0);
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signal VIDEO_B_WIDE : std_logic_vector(7 downto 0);
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-- CPU
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SIGNAL CPU_6502_RESET : STD_LOGIC;
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SIGNAL CPU_ADDR : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL CPU_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL CPU_FETCH : STD_LOGIC;
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SIGNAL IRQ_n : STD_LOGIC;
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SIGNAL NMI_n : STD_LOGIC;
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SIGNAL R_W_N : STD_LOGIC;
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-- CLOCKING STUFF
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-- TODO - review/explain what all these are for
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SIGNAL CPU_SHARED_ENABLE : STD_LOGIC;
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SIGNAL ENABLE_179_MEMWAIT : STD_LOGIC;
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SIGNAL ANTIC_ENABLE_179 : STD_LOGIC;
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-- POKEY
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SIGNAL POKEY_IRQ : STD_LOGIC;
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SIGNAL POKEY_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL CACHE_POKEY_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL POKEY_WRITE_ENABLE : STD_LOGIC;
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signal POKEY1_CHANNEL0 : std_logic_vector(3 downto 0);
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signal POKEY1_CHANNEL1 : std_logic_vector(3 downto 0);
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signal POKEY1_CHANNEL2 : std_logic_vector(3 downto 0);
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signal POKEY1_CHANNEL3 : std_logic_vector(3 downto 0);
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-- MEMORY IS READY - input to all devices
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SIGNAL MEMORY_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL MEMORY_READY_ANTIC : STD_LOGIC;
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SIGNAL MEMORY_READY_CPU : STD_LOGIC;
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SIGNAL WRITE_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL WIDTH_16BIT_ACCESS : STD_LOGIC;
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SIGNAL WIDTH_32BIT_ACCESS : STD_LOGIC;
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SIGNAL WIDTH_8BIT_ACCESS : STD_LOGIC;
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-- PBI
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SIGNAL PBI_ADDR_INT : std_logic_vector(15 downto 0);
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BEGIN
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PBI_WIDTH_8bit_ACCESS <= WIDTH_8bit_access;
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PBI_WIDTH_16bit_ACCESS <= WIDTH_16bit_access;
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PBI_WIDTH_32bit_ACCESS <= WIDTH_32bit_access;
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PBI_WRITE_DATA <= WRITE_DATA;
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PBI_SNOOP_DATA <= MEMORY_DATA;
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enables : entity work.shared_enable
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GENERIC MAP(cycle_length => cycle_length)
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PORT MAP(CLK => CLK,
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RESET_N => RESET_N,
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MEMORY_READY_CPU => MEMORY_READY_CPU,
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MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
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ANTIC_REFRESH => ANTIC_REFRESH_CYCLE,
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PAUSE_6502 => HALT,
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THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
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ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
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oldcpu_enable => ENABLE_179_MEMWAIT,
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CPU_ENABLE_OUT => CPU_SHARED_ENABLE);
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CPU_6502_RESET <= NOT(RESET_N);
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cpu6502 : entity work.cpu
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PORT MAP(CLK => CLK,
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RESET => CPU_6502_RESET,
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ENABLE => RESET_N,
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IRQ_n => IRQ_n,
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NMI_n => NMI_n,
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MEMORY_READY => MEMORY_READY_CPU,
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THROTTLE => CPU_SHARED_ENABLE,
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RDY => ANTIC_RDY,
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DI => MEMORY_DATA(7 DOWNTO 0),
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R_W_n => R_W_N,
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CPU_FETCH => CPU_FETCH,
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A => CPU_ADDR,
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DO => CPU_DO);
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antic1 : entity work.antic
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GENERIC MAP(cycle_length => cycle_length)
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PORT MAP(CLK => CLK,
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WR_EN => ANTIC_WRITE_ENABLE,
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RESET_N => RESET_N,
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MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
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MEMORY_READY_CPU => MEMORY_READY_CPU,
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ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
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PAL => '0',
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lightpen => '0',
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ADDR => PBI_ADDR_INT(3 DOWNTO 0),
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CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
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MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
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NMI_N_OUT => NMI_n,
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ANTIC_READY => ANTIC_RDY,
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COLOUR_CLOCK_ORIGINAL_OUT => ANTIC_ORIGINAL_COLOUR_CLOCK_OUT,
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COLOUR_CLOCK_OUT => ANTIC_COLOUR_CLOCK_OUT,
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HIGHRES_COLOUR_CLOCK_OUT => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
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dma_fetch_out => ANTIC_FETCH,
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hcount_out => hcount_temp,
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vcount_out => vcount_temp,
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refresh_out => ANTIC_REFRESH_CYCLE,
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AN => ANTIC_AN,
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DATA_OUT => ANTIC_DO,
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dma_address_out => ANTIC_ADDR);
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pokey_mixer : entity work.pokey_mixer_mux
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PORT MAP(CLK => CLK,
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ENABLE_179 => ENABLE_179_MEMWAIT,
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GTIA_SOUND => '0',
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SIO_AUDIO => "00000000",
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CHANNEL_L_0 => POKEY1_CHANNEL0,
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CHANNEL_L_1 => POKEY1_CHANNEL1,
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CHANNEL_L_2 => POKEY1_CHANNEL2,
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CHANNEL_L_3 => POKEY1_CHANNEL3,
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COVOX_CHANNEL_L_0 => (others=>'0'),
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COVOX_CHANNEL_L_1 => (others=>'0'),
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CHANNEL_R_0 => POKEY1_CHANNEL0,
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CHANNEL_R_1 => POKEY1_CHANNEL1,
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CHANNEL_R_2 => POKEY1_CHANNEL2,
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CHANNEL_R_3 => POKEY1_CHANNEL3,
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COVOX_CHANNEL_R_0 => (others=>'0'),
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COVOX_CHANNEL_R_1 => (others=>'0'),
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VOLUME_OUT_L => AUDIO_L,
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VOLUME_OUT_R => AUDIO_R);
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-- TODO, this is freddy, replace with 5200 equiv rather than generic
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-- Also remove dma logic from here if possible
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mmu1 : entity work.address_decoder
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GENERIC MAP(low_memory => low_memory, system => 10, internal_ram => internal_ram)
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PORT MAP(CLK => CLK,
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CPU_FETCH => CPU_FETCH,
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CPU_WRITE_N => R_W_N,
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ANTIC_FETCH => ANTIC_FETCH,
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DMA_FETCH => DMA_FETCH,
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DMA_READ_ENABLE => DMA_READ_ENABLE,
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DMA_32BIT_WRITE_ENABLE => DMA_32BIT_WRITE_ENABLE,
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DMA_16BIT_WRITE_ENABLE => DMA_16BIT_WRITE_ENABLE,
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DMA_8BIT_WRITE_ENABLE => DMA_8BIT_WRITE_ENABLE,
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RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,
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ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
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PBI_REQUEST_COMPLETE => PBI_REQUEST_COMPLETE,
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--PBI_TAKEOVER => PBI_TAKEOVER,
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--PBI_RELEASE => PBI_RELEASE,
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PBI_TAKEOVER => '0',
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PBI_RELEASE => '0',
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--PBI_MPD_N => PBI_MPD_N,
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PBI_MPD_N => '1',
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PBI_DATA => "11111111",
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reset_n => RESET_N,
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CART_RD5 => '0',
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SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
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ANTIC_ADDR => ANTIC_ADDR,
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ANTIC_DATA => ANTIC_DO,
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CACHE_ANTIC_DATA => CACHE_ANTIC_DO,
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CPU_ADDR => CPU_ADDR,
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CPU_WRITE_DATA => CPU_DO,
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GTIA_DATA => GTIA_DO,
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CACHE_GTIA_DATA => CACHE_GTIA_DO,
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PIA_DATA => (others=>'0'),
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POKEY_DATA => POKEY_DO,
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CACHE_POKEY_DATA => CACHE_POKEY_DO,
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PORTB => (others=>'0'),
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RAM_DATA => RAM_DO,
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ram_select => "000",
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ROM_DATA => ROM_DO,
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SDRAM_DATA => SDRAM_DO,
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DMA_ADDR => DMA_ADDR,
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DMA_WRITE_DATA => DMA_WRITE_DATA,
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MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
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MEMORY_READY_DMA => MEMORY_READY_DMA,
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MEMORY_READY_CPU => MEMORY_READY_CPU,
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GTIA_WR_ENABLE => GTIA_WRITE_ENABLE,
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POKEY_WR_ENABLE => POKEY_WRITE_ENABLE,
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ANTIC_WR_ENABLE => ANTIC_WRITE_ENABLE,
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PIA_WR_ENABLE => open,
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PIA_RD_ENABLE => open,
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RAM_WR_ENABLE => RAM_WRITE_ENABLE,
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ROM_WR_ENABLE => ROM_WRITE_ENABLE,
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PBI_WR_ENABLE => PBI_WRITE_ENABLE,
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RAM_REQUEST => RAM_REQUEST,
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ROM_REQUEST => ROM_REQUEST,
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PBI_REQUEST => PBI_REQUEST,
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WIDTH_8bit_ACCESS => WIDTH_8BIT_ACCESS,
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WIDTH_16bit_ACCESS => WIDTH_16BIT_ACCESS,
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WIDTH_32bit_ACCESS => WIDTH_32BIT_ACCESS,
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SDRAM_READ_EN => SDRAM_READ_ENABLE,
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SDRAM_WRITE_EN => SDRAM_WRITE_ENABLE,
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SDRAM_REQUEST => SDRAM_REQUEST,
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MEMORY_DATA => MEMORY_DATA,
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PBI_ADDR => PBI_ADDR_INT,
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RAM_ADDR => RAM_ADDR,
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ROM_ADDR => ROM_ADDR,
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SDRAM_ADDR => SDRAM_ADDR,
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WRITE_DATA => WRITE_DATA,
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d6_wr_enable => open,
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cart_select => (others=>'0'),
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rom_in_ram => ROM_IN_RAM,
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freezer_enable => '0',
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freezer_activate => '0');
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pokey1 : entity work.pokey
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PORT MAP(CLK => CLK,
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ENABLE_179 => ENABLE_179_MEMWAIT,
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WR_EN => POKEY_WRITE_ENABLE,
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RESET_N => RESET_N,
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SIO_IN1 => SIO_RXD,
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SIO_IN2 => '1',
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SIO_IN3 => '1',
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ADDR => PBI_ADDR_INT(3 DOWNTO 0),
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|
DATA_IN => WRITE_DATA(7 DOWNTO 0),
|
|
keyboard_response => KEYBOARD_RESPONSE,
|
|
POT_IN => POT_IN,
|
|
IRQ_N_OUT => POKEY_IRQ,
|
|
SIO_OUT1 => SIO_TXD,
|
|
SIO_OUT2 => open,
|
|
SIO_OUT3 => open,
|
|
POT_RESET => POT_RESET,
|
|
CHANNEL_0_OUT => POKEY1_CHANNEL0,
|
|
CHANNEL_1_OUT => POKEY1_CHANNEL1,
|
|
CHANNEL_2_OUT => POKEY1_CHANNEL2,
|
|
CHANNEL_3_OUT => POKEY1_CHANNEL3,
|
|
DATA_OUT => POKEY_DO,
|
|
keyboard_scan => KEYBOARD_SCAN);
|
|
|
|
|
|
gtia1 : entity work.gtia
|
|
PORT MAP(CLK => CLK,
|
|
WR_EN => GTIA_WRITE_ENABLE,
|
|
ANTIC_FETCH => ANTIC_FETCH, -- for first pmg fetch
|
|
CPU_ENABLE_ORIGINAL => ENABLE_179_MEMWAIT, -- for subsequent pmg fetches
|
|
RESET_N => RESET_N,
|
|
PAL => '0',
|
|
ENABLE_179 => ENABLE_179_MEMWAIT,
|
|
COLOUR_CLOCK_ORIGINAL => ANTIC_ORIGINAL_COLOUR_CLOCK_OUT,
|
|
COLOUR_CLOCK => ANTIC_COLOUR_CLOCK_OUT,
|
|
COLOUR_CLOCK_HIGHRES => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
|
|
CONSOL_OUT => CONSOL_OUT,
|
|
CONSOL_IN => CONSOL_IN,
|
|
TRIG => GTIA_TRIG,
|
|
ADDR => PBI_ADDR_INT(4 DOWNTO 0),
|
|
AN => ANTIC_AN,
|
|
CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
|
|
MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
|
|
VSYNC => VIDEO_VS,
|
|
HSYNC => VIDEO_HS,
|
|
CSYNC => VIDEO_CS,
|
|
BLANK => VIDEO_BLANK,
|
|
BURST => VIDEO_BURST,
|
|
START_OF_FIELD => VIDEO_START_OF_FIELD,
|
|
ODD_LINE => VIDEO_ODD_LINE,
|
|
COLOUR_out => COLOUR,
|
|
DATA_OUT => GTIA_DO);
|
|
|
|
-- colour palette
|
|
|
|
gen_palette_none : if palette=0 generate
|
|
VIDEO_B_WIDE <= COLOUR;
|
|
VIDEO_R_WIDE <= (others => '0');
|
|
VIDEO_G_WIDE <= (others => '0');
|
|
end generate;
|
|
|
|
gen_palette_on : if palette=1 generate
|
|
palette4 : entity work.gtia_palette
|
|
port map (PAL=>'0', ATARI_COLOUR=>COLOUR, R_next=>VIDEO_R_WIDE, G_next=>VIDEO_G_WIDE, B_next=>VIDEO_B_WIDE);
|
|
end generate;
|
|
|
|
VIDEO_R(video_bits-1 downto 0) <= VIDEO_R_WIDE(7 downto 8-video_bits);
|
|
VIDEO_G(video_bits-1 downto 0) <= VIDEO_G_WIDE(7 downto 8-video_bits);
|
|
VIDEO_B(video_bits-1 downto 0) <= VIDEO_B_WIDE(7 downto 8-video_bits);
|
|
|
|
-- Combine irq - only one here!
|
|
IRQ_n <= POKEY_IRQ;
|
|
|
|
-- TODO - generic ram infer?
|
|
pokey1_mirror : entity work.reg_file
|
|
generic map(BYTES=>16,WIDTH=>4)
|
|
port map(
|
|
CLK => CLK,
|
|
ADDR => PBI_ADDR_INT(3 downto 0),
|
|
DATA_IN => WRITE_DATA(7 downto 0),
|
|
WR_EN => POKEY_WRITE_ENABLE,
|
|
DATA_OUT => CACHE_POKEY_DO
|
|
);
|
|
|
|
gtia_mirror : entity work.reg_file
|
|
generic map(BYTES=>32,WIDTH=>5)
|
|
port map(
|
|
CLK => CLK,
|
|
ADDR => PBI_ADDR_INT(4 downto 0),
|
|
DATA_IN => WRITE_DATA(7 downto 0),
|
|
WR_EN => GTIA_WRITE_ENABLE,
|
|
DATA_OUT => CACHE_GTIA_DO
|
|
);
|
|
|
|
antic_mirror : entity work.reg_file
|
|
generic map(BYTES=>16,WIDTH=>4)
|
|
port map(
|
|
CLK => CLK,
|
|
ADDR => PBI_ADDR_INT(3 downto 0),
|
|
DATA_IN => WRITE_DATA(7 downto 0),
|
|
WR_EN => ANTIC_WRITE_ENABLE,
|
|
DATA_OUT => CACHE_ANTIC_DO
|
|
);
|
|
|
|
-- outputs
|
|
PBI_ADDR <= PBI_ADDR_INT;
|
|
ANTIC_REFRESH <= ANTIC_REFRESH_CYCLE;
|
|
|
|
END bdf_type;
|