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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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library std_developerskit ; -- used for to_string
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-- use std_developerskit.std_iopak.all;
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entity sallymax_tb is
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end;
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architecture rtl of sallymax_tb is
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constant CLK_BUS_PERIOD : time := 1 us / (1.79);
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constant CLK_FAST_PERIOD : time := 1 us / (1.79*32);
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signal reset_n : std_logic;
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signal clk_phi0 : std_logic;
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signal clk_fast : std_logic;
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signal clk_routed : std_logic;
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signal bus_addr : std_logic_vector(15 downto 0);
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signal bus_data : std_logic_vector(7 downto 0);
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signal bus_data_out : std_logic_vector(7 downto 0);
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signal bus_drive : std_logic;
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signal bus_rw : std_logic;
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signal bus_phi1 : std_logic;
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signal bus_phi2 : std_logic;
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signal slave_request : std_logic;
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signal slave_addr : std_logic_vector(15 downto 0);
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signal slave_data_in : std_logic_vector(7 downto 0);
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signal slave_data_out : std_logic_vector(7 downto 0);
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signal slave_rw_n : std_logic;
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signal slave_cs : std_logic;
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signal halt_n : std_logic;
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begin
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p_clk_gen_b : process
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begin
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clk_phi0 <= '1';
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wait for CLK_BUS_PERIOD/2;
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clk_phi0 <= '0';
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wait for CLK_BUS_PERIOD - (CLK_BUS_PERIOD/2 );
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end process;
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p_clk_gen_f : process
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begin
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clk_fast <= '1';
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wait for CLK_FAST_PERIOD/2;
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clk_fast <= '0';
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wait for CLK_FAST_PERIOD - (CLK_FAST_PERIOD/2 );
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end process;
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reset_n <= '0', '1' after 1000ns;
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thebigone: entity work.sallymax
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port map
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(
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PHI0 => clk_phi0,
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RST_N => reset_n,
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CLK_OUT => CLK_ROUTED,
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CLK_SLOW => CLK_ROUTED,
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A => BUS_ADDR,
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D => BUS_DATA,
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W_N => BUS_RW,
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RDY => '1',
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HALT_N => halt_n,
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NMI_N => '1',
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IRQ_N => '1',
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S0 => '1',
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phi2 => bus_phi2,
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phi1 => bus_phi1
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);
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busadapt : entity work.slave_timing_6502
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port map
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(
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CLK => clk_fast,
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RESET_N => reset_n,
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PHI2 => bus_phi2,
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bus_addr => bus_addr,
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bus_data => bus_data,
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bus_cs => '1',
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bus_rw_n => bus_rw,
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bus_data_out => bus_data_out,
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bus_drive => bus_drive,
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BUS_REQUEST => slave_request,
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ADDR_IN => slave_addr,
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DATA_IN => slave_data_in,
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RW_N => slave_rw_n,
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CS => slave_cs,
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ENABLE_CYCLE => open,
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DATA_OUT => slave_data_out
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);
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bus_data <= bus_data_out when bus_drive='1' else (others=>'Z');
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process
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begin
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halt_n <= '1';
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wait until reset_n='1';
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wait until slave_request='1';
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slave_data_out <= x"00";
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wait until slave_request='0';
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wait until slave_request='1';
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slave_data_out <= x"e0";
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wait until slave_request='0';
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wait until slave_request='1';
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slave_data_out <= x"ea";
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wait until slave_request='0';
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wait until slave_request='1';
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slave_data_out <= x"ea";
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wait until slave_request='0';
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wait until slave_request='1';
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slave_data_out <= x"ea";
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wait until slave_request='0';
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wait until slave_request='1';
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slave_data_out <= x"ea";
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wait until slave_request='0';
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wait until slave_request='1';
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slave_data_out <= x"ea";
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wait until slave_request='0';
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wait until slave_request='1';
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slave_data_out <= x"ea";
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wait until slave_request='0';
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wait until slave_request='1';
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slave_data_out <= x"ea";
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wait until slave_request='0';
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wait until slave_request='1';
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slave_data_out <= x"ea";
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wait until slave_request='0';
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wait until slave_request='1';
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slave_data_out <= x"ea";
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wait until slave_request='0';
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wait until bus_phi2='1';
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wait until bus_phi2='0';
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wait for 200ns;
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halt_n <= '0';
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wait for 20us;
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end process;
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end rtl;
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