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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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library std_developerskit ; -- used for to_string
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-- use std_developerskit.std_iopak.all;
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entity pokeymax_tb is
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end;
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architecture rtl of pokeymax_tb is
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constant CLK_BUS_PERIOD : time := 1 us / (1.79*32);
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signal reset_n : std_logic;
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signal clk_cart : std_logic;
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signal clk_routed : std_logic;
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signal BUS_ADDR: std_logic_vector(15 downto 0);
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signal BUS_DATA: std_logic_vector(7 downto 0);
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signal BUS_PHI2: std_logic;
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signal BUS_CS_N: std_logic;
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signal BUS_RW: std_logic;
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-- 6502 bus other side
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signal enable_179_early : std_logic;
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signal cart_request : std_logic;
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signal pbi_addr_out : std_logic_vector(15 downto 0);
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signal cart_data_write : std_logic_vector(7 downto 0);
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signal pbi_write_enable : std_logic;
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signal CS_N : std_logic;
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signal cart_data_read : std_logic_vector(7 downto 0);
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signal cart_complete : std_logic;
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signal bus_data_in : std_logic_vector(7 downto 0);
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signal bus_data_out : std_logic_vector(7 downto 0);
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signal bus_data_oe : std_logic;
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signal bus_addr_out : std_logic_vector(15 downto 0);
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signal bus_addr_oe : std_logic;
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signal bus_write_n : std_logic;
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signal bus_control_oe : std_logic;
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signal bus_cs_n_out : std_logic;
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signal paddle : std_logic_vector(7 downto 0);
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begin
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p_clk_gen_b : process
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begin
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clk_cart <= '1';
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wait for CLK_BUS_PERIOD/2;
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clk_cart <= '0';
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wait for CLK_BUS_PERIOD - (CLK_BUS_PERIOD/2 );
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end process;
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reset_n <= '0', '1' after 1000ns;
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process_enable : process
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begin
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '1'; -- HERE!
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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end process;
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process_setup_sram : process
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begin
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cart_request <= '0';
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pbi_addr_out <= (others=>'0');
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cart_data_write <= (others=>'0');
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pbi_write_enable <= '0';
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wait for 6000ns;
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wait until enable_179_early'event and enable_179_early = '1';
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cart_request <= '1';
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pbi_addr_out <= x"D200";
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cart_data_write <= x"fe";
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pbi_write_enable <= '1';
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wait until enable_179_early'event and enable_179_early = '1';
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cart_request <= '1';
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pbi_write_enable <= '0';
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wait until enable_179_early'event and enable_179_early = '1';
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pbi_addr_out <= x"D201";
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wait until enable_179_early'event and enable_179_early = '1';
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--cart_data_write <= x"ec";
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cart_data_write <= x"ef";
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pbi_write_enable <= '1';
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wait until enable_179_early'event and enable_179_early = '1';
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cart_request <= '1';
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pbi_addr_out <= x"D208";
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cart_data_write <= x"40";
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pbi_write_enable <= '1';
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wait until enable_179_early'event and enable_179_early = '1';
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pbi_write_enable <= '0';
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wait until enable_179_early'event and enable_179_early = '1';
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cart_request <= '1';
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pbi_addr_out <= x"D20a";
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wait until enable_179_early'event and enable_179_early = '1';
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wait until enable_179_early'event and enable_179_early = '1';
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wait until enable_179_early'event and enable_179_early = '1';
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wait until enable_179_early'event and enable_179_early = '1';
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wait until enable_179_early'event and enable_179_early = '1';
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wait until enable_179_early'event and enable_179_early = '1';
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wait until enable_179_early'event and enable_179_early = '1';
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wait until enable_179_early'event and enable_179_early = '1';
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wait until enable_179_early'event and enable_179_early = '1';
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wait until enable_179_early'event and enable_179_early = '1';
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cart_request <= '0';
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wait until enable_179_early'event and enable_179_early = '1';
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cart_request <= '1';
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pbi_addr_out <= x"D20f";
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cart_data_write <= x"03";
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pbi_write_enable <= '1';
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wait until enable_179_early'event and enable_179_early = '1';
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cart_request <= '0';
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pbi_write_enable <= '0';
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wait for 100000000us;
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end process;
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thebigone: entity work.pokeymax
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port map
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(
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PHI2 => BUS_PHI2,
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CLK_OUT => CLK_ROUTED,
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CLK_SLOW => CLK_ROUTED,
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A => BUS_ADDR(4 downto 0),
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D => BUS_DATA,
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CS0_N => BUS_CS_N,
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CS1 => not(BUS_CS_N),
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W_N => BUS_RW,
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IRQ => open,
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SOD => open,
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SID => '1',
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ACLK => open,
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BCLK => open,
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AUD => open,
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PADDLE => paddle,
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KEYBOARD_RESPONSE => "11"
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);
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paddle <= (others=>'0');
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bus_adaptor : ENTITY work.timing6502
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GENERIC MAP
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(
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CYCLE_LENGTH => 32,
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CONTROl_BITS => 1
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)
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PORT MAP
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(
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CLK => clk_cart,
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RESET_N => reset_n,
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-- FPGA side
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ENABLE_179_EARLY =>enable_179_early,
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REQUEST => cart_request,
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ADDR_IN => pbi_addr_out,
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DATA_IN => cart_data_write,
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WRITE_IN => pbi_write_enable,
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CONTROL_N_IN(0) => CS_N,
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DATA_OUT => cart_data_read,
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COMPLETE => cart_complete,
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-- 6502 side
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BUS_DATA_IN => BUS_DATA,
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BUS_PHI1 => open,
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BUS_PHI2 => BUS_PHI2,
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BUS_SUBCYCLE => open,
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BUS_ADDR_OUT => bus_addr_out,
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BUS_ADDR_OE => bus_addr_oe,
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BUS_DATA_OUT => bus_data_out,
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BUS_DATA_OE => bus_data_oe,
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BUS_WRITE_N => BUS_RW,
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BUS_CONTROL_OE => BUS_CONTROL_OE,
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BUS_CONTROL_N(0) => BUS_CS_N_OUT
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);
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BUS_ADDR <= bus_addr_out(15 downto 0) when bus_addr_oe='1' else (others=>'Z');
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BUS_DATA <= bus_data_out when bus_data_oe='1' else (others=>'Z');
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CS_N <= '0' when pbi_addr_out(15 downto 8)= x"D2" else '1';
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BUS_CS_N <= BUS_CS_N_OUT when BUS_CONTROL_OE='1' else 'Z';
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end rtl;
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