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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY int_osc IS
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PORT
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(
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clkout : out std_logic; -- clkout.clk
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oscena : in std_logic := '0' -- oscena.oscena
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);
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END int_osc;
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ARCHITECTURE vhdl OF int_osc IS
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constant CLK0_PERIOD : time := 1 us / (55);
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begin
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p_clk_gen_a : process
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begin
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clkout <= '1';
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wait for CLK0_PERIOD/2;
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clkout <= '0';
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wait for CLK0_PERIOD - (CLK0_PERIOD/2 );
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end process;
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end vhdl;
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