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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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use IEEE.STD_LOGIC_MISC.all;
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ENTITY slave_timing_6502 IS
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GENERIC (
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address_bits : integer
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);
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PORT (
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CLK: in std_logic;
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RESET_N: in std_logic;
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-- input from the cart port
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PHI2 : in std_logic; -- async to our clk (ish):-(
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bus_addr : in std_logic_vector(address_bits-1 downto 0);
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bus_data : in std_logic_vector(7 downto 0);
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bus_cs : in std_logic;
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bus_rw_n : in std_logic;
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-- output to the cart port
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bus_data_out : out std_logic_vector(7 downto 0);
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bus_drive : out std_logic;
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-- request for a memory bus cycle (read or write)
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BUS_REQUEST: out std_logic;
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ADDR_IN: out std_logic_vector(address_bits-1 downto 0);
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DATA_IN: out std_logic_vector(7 downto 0);
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RW_N: out std_logic;
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CS : out std_logic;
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ENABLE_CYCLE : out std_logic;
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ENABLE_DOUBLE_CYCLE : out std_logic;
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DATA_OUT: in std_logic_vector(7 downto 0); -- read_data
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DRIVE_DATA_OUT: in std_logic
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);
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END slave_timing_6502;
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ARCHITECTURE vhdl OF slave_timing_6502 IS
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signal PHI2_sync : std_logic;
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signal phi_edge_prev_next : std_logic;
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signal phi_edge_prev_reg: std_logic;
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signal bus_data_out_next : std_logic_vector(7 downto 0);
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signal bus_data_out_reg : std_logic_vector(7 downto 0);
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signal bus_drive_next : std_logic;
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signal bus_drive_reg : std_logic;
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signal state_reg : std_logic_vector(1 downto 0);
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signal state_next : std_logic_vector(1 downto 0);
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constant state_wait_addrctl : std_logic_vector(1 downto 0) := "01";
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constant state_write_request : std_logic_vector(1 downto 0) := "10";
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constant state_read_output : std_logic_vector(1 downto 0) := "11";
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signal internal_memory_request : std_logic;
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signal registered_read_data_next : std_logic_vector(7 downto 0);
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signal registered_read_data_reg : std_logic_vector(7 downto 0);
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signal registered_drive_bus_next : std_logic;
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signal registered_drive_bus_reg : std_logic;
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signal phi2_falling_edge : std_logic;
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signal phi2_rising_edge : std_logic;
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signal phi2_falling_edge_reg : std_logic;
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signal phi2_either_edge_reg : std_logic;
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signal phi_addr_reg : std_logic_vector(address_bits-1 downto 0);
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signal phi_cs_reg : std_logic;
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signal phi_rw_n_reg : std_logic;
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signal phi_data_reg : std_logic_vector(7 downto 0);
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begin
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-- phi2 half, phi2 is in sync properly within the atari, the out of sync stuff is a feature of the PBI buffer I believe
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process(phi2,reset_n)
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begin
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if (reset_n='0') then
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phi_data_reg <= (others=>'0');
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elsif (phi2'event and phi2='0') then -- falling edge
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phi_data_reg <= bus_data;
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end if;
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end process;
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process(phi2,reset_n)
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begin
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if (reset_n='0') then
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phi_addr_reg <= (others=>'0');
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phi_cs_reg <= '1';
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phi_rw_n_reg <= '1';
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elsif (phi2'event and phi2='1') then -- rising edge
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phi_addr_reg <= bus_addr;
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phi_cs_reg <= bus_cs;
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phi_rw_n_reg <= bus_rw_n;
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end if;
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end process;
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-- Fast half
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process(clk,reset_n)
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begin
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if (reset_n='0') then
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phi_edge_prev_reg <= '1';
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bus_data_out_reg <= (others=>'0');
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bus_drive_reg <= '0';
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registered_read_data_reg <= (others=>'0');
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registered_drive_bus_reg <= '0';
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phi2_falling_edge_reg <= '0';
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phi2_either_edge_reg <= '0';
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state_reg <= state_wait_addrctl;
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elsif (clk'event and clk='1') then
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phi_edge_prev_reg <= phi_edge_prev_next;
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bus_data_out_reg <= bus_data_out_next;
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bus_drive_reg <= bus_drive_next;
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registered_read_data_reg <= registered_read_data_next;
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registered_drive_bus_reg <= registered_drive_bus_next;
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phi2_falling_edge_reg <= phi2_falling_edge;
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phi2_either_edge_reg <= phi2_falling_edge or phi2_rising_edge;
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state_reg <= state_next;
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end if;
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end process;
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synchronizer_phi : entity work.synchronizer
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port map (clk=>clk, raw=>PHI2, sync=>PHI2_SYNC);
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phi_edge_prev_next <= phi2_sync;
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phi2_falling_edge <= phi_edge_prev_reg and not(phi2_sync);
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phi2_rising_edge <= not(phi_edge_prev_reg) and phi2_sync;
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process(registered_read_data_reg, data_out,
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registered_drive_bus_reg, drive_data_out,
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bus_drive_reg,bus_data_out_reg,
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phi2_rising_edge,
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phi2_falling_edge,
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phi_cs_reg,
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phi_rw_n_reg,
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state_reg)
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begin
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-- maintain snap (only read bus when safe!)
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internal_memory_request <= '0';
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bus_data_out_next <= bus_data_out_reg;
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bus_drive_next <= bus_drive_reg;
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registered_read_data_next <= registered_read_data_reg;
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registered_drive_bus_next <= registered_drive_bus_reg;
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-- TODO: Drive off rise/fall of phi2
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-- delays should be based off tsu/th times from data shet
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-- I heard the data from cpu is not always stable on writes at the clock edge, might need to have a short buffer and wait for edge then read etc.
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-- IN:
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-- RW/ADDR tSU (130ns), tH (30ns)
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-- CS tSU (50ns), tH (30ns)
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-- D tSU (130ns), tH (10ns)
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-- OUT:
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-- D tSU (50ns), tH (20ns)
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-- IRQ tDELAY (350ns??)
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-- write timing
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-- r/w read on rising edge of phi2 -> HELD until falling edge of phi2 + tH
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-- CS read on rising edge of phi2 -> HELD until falling edge of phi2 + tH
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-- addr read on rising edge of phi2 -> HELD until phi2 is risen
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-- read timing
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-- r/w similar
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-- cs similar
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-- drive data tDSR before falling edge - I guess it makes sense to drive it as early after phi2 risen as possible
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-- concern: hold times are known not to be respected, best to read prior to phi2 by some ns
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-- issue with that: we don't know the clock
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-- solution: trigger read/write on phi2 edge, but... use data from a cycle before -> 1 cycle 17ns.
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-- current solution ->
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-- phi2 edge + 13 cycles -> snap addr,rw_n,cs_n -> 232ns
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-- read: then runs pokey, then output from 22->33 cycles -> 392 to 590ns
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-- write: snap bus at cycle 28 -> 500ns
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-- pokey run at 553ns
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-- which is fine for in Atari 8-bit, but not arcade...
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-- since cycle length:
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-- 1.00MHz -> 1000ns
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-- 1.25MHz -> 800ns
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-- 1.50MHz -> 666ns
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-- 1.77MHz -> 564ns
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-- 1.79MHz -> 558ns
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-- solution is to measure
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-- LLLLLLLHHHHHHH
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-- XXAAAAAAAAAAAA
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-- XXXXXXXXXXDDDD
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state_next <= state_reg;
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case (state_reg) is
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when state_wait_addrctl =>
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registered_read_data_next <= data_out;
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registered_drive_bus_next <= drive_data_out;
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if (phi2_rising_edge='1' and phi_cs_reg='1') then
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-- snap control signals, should be stable by now
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if (phi_rw_n_reg='1') then -- read
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internal_memory_request <= '1';
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state_next <= state_read_output;
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else
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state_next <= state_write_request;
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end if;
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end if;
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when state_write_request =>
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if (phi2_falling_edge='1') then
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internal_memory_request <= '1';
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state_next <= state_wait_addrctl;
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end if;
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when state_read_output =>
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bus_data_out_next <= registered_read_data_reg;
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bus_drive_next <= not(phi2_falling_edge) and registered_drive_bus_reg;
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if (phi2_falling_edge='1') then
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state_next <= state_wait_addrctl;
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end if;
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when others =>
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end case;
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end process;
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bus_data_out <= bus_data_out_reg;
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bus_drive <= bus_drive_reg;
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bus_request <= internal_memory_request;
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addr_in <= phi_addr_reg;
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data_in <= phi_data_reg;
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rw_n <= phi_rw_n_reg;
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CS <= phi_cs_reg;
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enable_cycle <= phi2_falling_edge_reg;
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enable_double_cycle <= phi2_either_edge_reg;
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end vhdl;
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