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---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY pokey_countdown_timer IS
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generic(UNDERFLOW_DELAY : natural := 3);
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PORT
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(
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CLK : IN STD_LOGIC;
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ENABLE : IN STD_LOGIC;
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ENABLE_UNDERFLOW : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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WR_EN : IN STD_LOGIC;
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DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
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DATA_OUT : OUT STD_LOGIC
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);
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END pokey_countdown_timer;
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ARCHITECTURE vhdl OF pokey_countdown_timer IS
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component delay_line IS
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generic(COUNT : natural := 1);
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PORT
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(
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CLK : IN STD_LOGIC;
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SYNC_RESET : IN STD_LOGIC;
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DATA_IN : IN STD_LOGIC;
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ENABLE : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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DATA_OUT : OUT STD_LOGIC
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);
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END component;
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function To_Std_Logic(L: BOOLEAN) return std_ulogic is
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begin
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if L then
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return('1');
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else
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return('0');
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end if;
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end function To_Std_Logic;
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signal count_reg : std_logic_vector(7 downto 0);
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signal count_next: std_logic_vector(7 downto 0);
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signal underflow : std_logic;
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signal count_command : std_logic_vector(1 downto 0);
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signal underflow_command: std_logic_vector(1 downto 0);
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BEGIN
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-- Instantiate delay (provides output)
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underflow0_delay : delay_line
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generic map (COUNT=>UNDERFLOW_DELAY)
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port map(clk=>clk,sync_reset=>wr_en,data_in=>underflow,enable=>ENABLE_UNDERFLOW,reset_n=>reset_n,data_out=>data_out);
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-- register
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process(clk,reset_n)
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begin
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if (reset_N = '0') then
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count_reg <= (others=>'0');
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elsif (clk'event and clk='1') then
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count_reg <= count_next;
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end if;
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end process;
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-- count down on enable
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process(count_reg,enable,wr_en,count_command,data_in)
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begin
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count_command <= enable&wr_en;
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case count_command is
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when "10" =>
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count_next <= std_logic_vector(unsigned(count_reg) -1);
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when "01"|"11" =>
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count_next <= data_in;
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when others =>
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count_next <= count_reg;
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end case;
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end process;
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-- underflow
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process(count_reg,enable,underflow_command)
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begin
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underflow_command <= enable & To_Std_Logic(count_reg = X"00");
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case underflow_command is
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when "11" =>
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underflow <= '1';
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when others =>
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underflow <= '0';
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end case;
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end process;
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END vhdl;
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