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component flash is
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port (
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clock : in std_logic := 'X'; -- clk
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avmm_csr_addr : in std_logic := 'X'; -- address
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avmm_csr_read : in std_logic := 'X'; -- read
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avmm_csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
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avmm_csr_write : in std_logic := 'X'; -- write
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avmm_csr_readdata : out std_logic_vector(31 downto 0); -- readdata
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avmm_data_addr : in std_logic_vector(15 downto 0) := (others => 'X'); -- address
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avmm_data_read : in std_logic := 'X'; -- read
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avmm_data_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
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avmm_data_write : in std_logic := 'X'; -- write
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avmm_data_readdata : out std_logic_vector(31 downto 0); -- readdata
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avmm_data_waitrequest : out std_logic; -- waitrequest
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avmm_data_readdatavalid : out std_logic; -- readdatavalid
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avmm_data_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
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reset_n : in std_logic := 'X' -- reset_n
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);
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end component flash;
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