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---------------------------------------------------------------------------
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-- (c) 2020 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY SID_oscillator IS
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PORT
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(
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CLK : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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ENABLE : IN STD_LOGIC;
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BITS_OUT : OUT STD_LOGIC_VECTOR(11 downto 0);
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TEST : IN STD_LOGIC;
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SYNC_IN : IN STD_LOGIC;
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SYNC_OUT : OUT STD_LOGIC;
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LFSR_ENABLE : OUT STD_LOGIC;
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CHANGING : OUT STD_LOGIC;
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ADJ : IN STD_LOGIC_VECTOR(15 downto 0)
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);
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END SID_oscillator;
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ARCHITECTURE vhdl OF SID_oscillator IS
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signal count_reg: unsigned(23 downto 0);
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signal count_next: unsigned(23 downto 0);
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signal lfsr_enable_shift_reg: std_logic_vector(1 downto 0);
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signal lfsr_enable_shift_next: std_logic_vector(1 downto 0);
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BEGIN
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-- register
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process(clk, reset_n)
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begin
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if (reset_n = '0') then
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count_reg <= (others=>'0');
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lfsr_enable_shift_reg <= (others=>'0');
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elsif (clk'event and clk='1') then
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count_reg <= count_next;
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lfsr_enable_shift_reg <= lfsr_enable_shift_next;
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end if;
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end process;
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-- next state
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process(count_reg,count_next,enable,adj,sync_in,test,lfsr_enable_shift_reg)
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variable count_inc : unsigned(23 downto 0);
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variable lfsr_enable_raw : std_logic;
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begin
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count_next <= count_reg;
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lfsr_enable_shift_next <= lfsr_enable_shift_reg;
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sync_out <= '0';
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changing <= '0';
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if (enable = '1') then
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count_inc := count_reg+resize(unsigned(adj),24);
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sync_out <= count_inc(23) and not(count_reg(23));
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lfsr_enable_raw := count_inc(19) and not(count_reg(19));
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if (sync_in='1' or test='1') then
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count_next <= (others=>'0');
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else
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count_next <= count_inc;
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end if;
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if (count_reg(23 downto 12) /= count_next(23 downto 12)) then
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changing <= '1';
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end if;
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lfsr_enable_shift_next <= lfsr_enable_shift_reg(0 downto 0)&lfsr_enable_raw;
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end if;
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end process;
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--output
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bits_out <= std_logic_vector(count_reg(23 downto 12));
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lfsr_enable <= lfsr_enable_shift_reg(1) and enable;
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END vhdl;
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