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---------------------------------------------------------------------------
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-- (c) 2020 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY PSG_mixer IS
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PORT
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(
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CLK : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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ENABLE : IN STD_LOGIC;
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NOISE : IN STD_LOGIC;
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CHANNEL : IN STD_LOGIC;
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NOISE_OFF : IN STD_LOGIC;
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TONE_OFF : IN STD_LOGIC;
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BIT_OUT : OUT STD_LOGIC
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);
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END PSG_mixer;
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ARCHITECTURE vhdl OF PSG_mixer IS
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signal bit_reg: std_logic;
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signal bit_next: std_logic;
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signal tone_reg: std_logic;
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signal tone_next: std_logic;
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BEGIN
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-- register
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process(clk, reset_n)
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begin
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if (reset_n = '0') then
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bit_reg <= '0';
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tone_reg <= '0';
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elsif (clk'event and clk='1') then
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bit_reg <= bit_next;
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tone_reg <= tone_next;
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end if;
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end process;
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-- next state
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process(tone_reg,bit_reg,enable,noise,channel,noise_off,tone_off)
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variable tone_comp : std_logic;
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begin
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tone_next <= tone_reg;
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bit_next <= bit_reg;
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if (enable = '1') then
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tone_comp := tone_reg xor channel;
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tone_next <= tone_comp;
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bit_next <= (noise or noise_off) and (tone_reg or tone_off);
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end if;
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end process;
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-- output
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bit_out <= bit_reg;
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END vhdl;
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