Project

General

Profile

{
"board": {
"active_layer": 0,
"active_layer_preset": "",
"auto_track_width": true,
"hidden_netclasses": [
"Default",
"LIN",
"Power_2"
],
"hidden_nets": [
"",
"/FPGA/TDI",
"/FPGA/TCK",
"/FPGA/TMS",
"Net-(U7-SW)",
"Net-(U6-NSTATUS)",
"/FPGA/OSC_CLOCK",
"Net-(U6-CONF_DONE)",
"unconnected-(U3-NC-Pad1)",
"unconnected-(U6-BB$7-PadK5)",
"unconnected-(U6-IO_UNUSED-PadE1)",
"unconnected-(U6-BB$13-PadL10)",
"unconnected-(U6-B$23-PadM13)",
"unconnected-(U6-IO_UNUSED-PadE1)_1",
"unconnected-(U6-B$8-PadM5)",
"unconnected-(U6-NC-PadD3)",
"unconnected-(U6-CLK1-PadH4)",
"unconnected-(U6-BB$14-PadK11)",
"unconnected-(U6-BB$16-PadK12)",
"unconnected-(U6-T$16-PadA10)",
"unconnected-(U6-IO_UNUSED-PadE1)_2",
"unconnected-(U6-BB$10-PadK7)",
"unconnected-(U6-NC-PadE2)",
"unconnected-(U6-B$17-PadM10)",
"unconnected-(U6-IO_UNUSED-PadE1)_3",
"unconnected-(U6-IO_UNUSED-PadE1)_4",
"unconnected-(U6-B$19-PadM11)",
"unconnected-(U6-IO_UNUSED-PadE1)_5",
"unconnected-(U6-IO_UNUSED-PadE1)_6",
"unconnected-(U6-T$20-PadA12)",
"unconnected-(U6-IO_UNUSED-PadE1)_7",
"/FPGA/TDO",
"unconnected-(U6-IO_UNUSED-PadE1)_8",
"unconnected-(U6-CLK0-PadH6)",
"unconnected-(U6-BB$21-PadJ6)",
"unconnected-(U6-IO_UNUSED-PadE1)_9",
"unconnected-(U6-B$21-PadM12)",
"unconnected-(U6-BB$22-PadJ7)",
"unconnected-(U6-JTAG_EN-PadE5)",
"unconnected-(U6-BB$6-PadL4)",
"unconnected-(U6-IO_UNUSED-PadE1)_10",
"unconnected-(U6-IO_UNUSED-PadE1)_11",
"unconnected-(U6-TB$2-PadD1)",
"unconnected-(U6-BB$20-PadJ5)",
"unconnected-(U6-B$13-PadM8)",
"unconnected-(U6-CRC_ERROR-PadD6)",
"unconnected-(U6-BB$12-PadK10)",
"unconnected-(U6-NC-PadD2)",
"unconnected-(U6-BB$15-PadL11)",
"unconnected-(U6-IO_UNUSED-PadE1)_12",
"unconnected-(U6-IO_UNUSED-PadE1)_13",
"unconnected-(U6-BB$11-PadK8)",
"unconnected-(U6-IO_UNUSED-PadE1)_14",
"unconnected-(U6-CONFIG_SEL-PadD7)",
"unconnected-(U6-T$21-PadB12)",
"unconnected-(U6-IO_UNUSED-PadE1)_15",
"unconnected-(U6-IO_UNUSED-PadE1)_16",
"unconnected-(U6-TB$5-PadD9)",
"unconnected-(U6-IO_UNUSED-PadE1)_17",
"unconnected-(U6-IO_UNUSED-PadE1)_18",
"unconnected-(U6-B$4-PadM3)",
"unconnected-(U6-IO_UNUSED-PadE1)_19",
"unconnected-(U6-IO_UNUSED-PadE1)_20",
"unconnected-(U6-B$11-PadM7)",
"unconnected-(U6-IO_UNUSED-PadE1)_21",
"unconnected-(U1-NC-Pad1)",
"/Bus drivers/FPGA.A1",
"/Bus drivers/EXT.A1",
"/Bus drivers/FPGA.A5",
"/Bus drivers/EXT.A3",
"/Bus drivers/EXT.A6",
"/Bus drivers/FPGA.A4",
"/Bus drivers/FPGA.A0",
"/Bus drivers/FPGA.A7",
"/Bus drivers/FPGA.A6",
"/Bus drivers/EXT.A4",
"/Bus drivers/EXT.A0",
"/Bus drivers/FPGA.A2",
"/Bus drivers/FPGA.A3",
"/Bus drivers/EXT.A5",
"/Bus drivers/EXT.A2",
"/Bus drivers/EXT.A7",
"/Bus drivers/A_OE_N",
"/Bus drivers/A_DIR",
"/Bus drivers/FPGA.A11",
"/Bus drivers/EXT.A13",
"/Bus drivers/FPGA.A13",
"/Bus drivers/EXT.A9",
"/Bus drivers/FPGA.A9",
"/Bus drivers/FPGA.A8",
"/Bus drivers/EXT.A15",
"/Bus drivers/FPGA.A15",
"/Bus drivers/FPGA.A14",
"/Bus drivers/FPGA.A10",
"/Bus drivers/EXT.A11",
"/Bus drivers/EXT.A8",
"/Bus drivers/FPGA.A12",
"/Bus drivers/EXT.A14",
"/Bus drivers/EXT.A12",
"/Bus drivers/EXT.A10",
"/Bus drivers/EXT.D6",
"/Bus drivers/D_DIR",
"/Bus drivers/FPGA.D3",
"/Bus drivers/FPGA.D4",
"/Bus drivers/EXT.D1",
"/Bus drivers/EXT.D2",
"/Bus drivers/FPGA.D7",
"/Bus drivers/FPGA.D2",
"/Bus drivers/EXT.D3",
"/Bus drivers/FPGA.D5",
"/Bus drivers/EXT.D0",
"/Bus drivers/FPGA.D1",
"/Bus drivers/EXT.D4",
"/Bus drivers/FPGA.D0",
"/Bus drivers/EXT.D5",
"/Bus drivers/D_OE_N",
"/Bus drivers/FPGA.D6",
"/Bus drivers/EXT.D7",
"unconnected-(U6-B$15-PadM9)",
"/antic_pins/EXT.C5",
"/antic_pins/EXT.C2",
"/antic_pins/EXT.C0",
"/antic_pins/EXT.C9",
"/antic_pins/EXT.C10",
"/antic_pins/EXT.C7",
"/antic_pins/EXT.C6",
"/antic_pins/EXT.C4",
"/antic_pins/EXT.C11",
"/antic_pins/EXT.C3",
"/antic_pins/EXT.C1",
"/antic_pins/EXT.C8",
"/antic_pins/EXT.C14",
"/antic_pins/EXT.C12",
"/antic_pins/EXT.C19",
"/antic_pins/EXT.C18",
"/antic_pins/EXT.C15",
"/antic_pins/EXT.C16",
"/antic_pins/EXT.C17",
"/antic_pins/EXT.C13",
"/level shifters/FPGA.C4",
"/level shifters/FPGA.C7",
"/level shifters/FPGA.C8",
"/level shifters/FPGA.C2",
"/level shifters/FPGA.C0",
"/level shifters/FPGA.C5",
"/level shifters/FPGA.C6",
"/level shifters/FPGA.C9",
"/level shifters/FPGA.C1",
"/level shifters/FPGA.C3",
"/level shifters/FPGA.C13",
"/level shifters/FPGA.C11",
"/level shifters/FPGA.C15",
"/level shifters/FPGA.C10",
"/level shifters/FPGA.C18",
"/level shifters/FPGA.C14",
"/level shifters/FPGA.C16",
"/level shifters/FPGA.C17",
"/level shifters/FPGA.C12",
"/level shifters/FPGA.C19",
"unconnected-(U6-IO_UNUSED-PadE1)_22",
"unconnected-(U6-IO_UNUSED-PadE1)_23",
"unconnected-(U6-BB$8-PadL5)",
"unconnected-(U6-B$6-PadM4)",
"Net-(U6-CLK2)",
"unconnected-(U6-B$2-PadM2)",
"unconnected-(U6-BB$17-PadL12)",
"unconnected-(U6-BB$5-PadL3)",
"unconnected-(U6-BB$3-PadK2)",
"unconnected-(U6-BB$27-PadJ12)",
"unconnected-(U6-IO_UNUSED-PadE1)_24",
"unconnected-(U6-BB$4-PadL2)",
"unconnected-(U6-IO_UNUSED-PadE1)_25",
"unconnected-(U6-T$17-PadB10)",
"unconnected-(U6-BB$23-PadJ8)",
"unconnected-(U6-BB$9-PadK6)",
"unconnected-(U6-IO_UNUSED-PadE1)_26",
"Net-(IC1-Pad35)"
],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"images": 0.6,
"pads": 1.0,
"shapes": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 0.6
},
"selection_filter": {
"dimensions": true,
"footprints": true,
"graphics": true,
"keepouts": true,
"lockedItems": false,
"otherItems": true,
"pads": true,
"text": true,
"tracks": true,
"vias": true,
"zones": true
},
"visible_items": [
"vias",
"footprint_text",
"footprint_anchors",
"ratsnest",
"grid",
"footprints_front",
"footprints_back",
"footprint_values",
"footprint_references",
"tracks",
"drc_errors",
"drawing_sheet",
"bitmaps",
"pads",
"zones",
"drc_warnings",
"locked_item_shadows",
"conflict_shadows",
"shapes"
],
"visible_layers": "00000000_00000000_000030f4_82000027",
"zone_display_mode": 0
},
"git": {
"repo_password": "",
"repo_type": "",
"repo_username": "",
"ssh_key": ""
},
"meta": {
"filename": "anticmax.kicad_prl",
"version": 5
},
"net_inspector_panel": {
"col_hidden": [
false,
false,
false,
false,
false,
false,
false,
false,
false,
false,
false,
false
],
"col_order": [
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11
],
"col_widths": [
162,
147,
91,
67,
91,
91,
91,
71,
91,
91,
91,
91
],
"custom_group_rules": [],
"expanded_rows": [],
"filter_by_net_name": true,
"filter_by_netclass": true,
"filter_text": "",
"group_by_constraint": false,
"group_by_netclass": false,
"show_unconnected_nets": false,
"show_zero_pad_nets": false,
"sort_ascending": true,
"sorting_column": 0
},
"open_jobsets": [],
"project": {
"files": []
},
"schematic": {
"selection_filter": {
"graphics": true,
"images": true,
"labels": true,
"lockedItems": false,
"otherItems": true,
"pins": true,
"symbols": true,
"text": true,
"wires": true
}
}
}
(4-4/12)