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<?xml version="1.0" encoding="UTF-8"?>
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<simPackage>
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<file
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path="osc_out_sim/altera_gpio_lite/altera_gpio_lite.sv"
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type="SYSTEM_VERILOG"
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library="osc_out" />
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<file
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path="osc_out_sim/altera_gpio_lite/mentor/altera_gpio_lite.sv"
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type="SYSTEM_VERILOG_ENCRYPT"
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library="osc_out"
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simulator="modelsim" />
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<file path="osc_out_sim/osc_out.vhd" type="VHDL" />
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<topLevel name="osc_out" />
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<deviceFamily name="max10" />
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</simPackage>
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