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---------------------------------------------------------------------------
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-- (c) 2017 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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USE ieee.math_real.ceil;
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USE ieee.math_real.log2;
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use IEEE.STD_LOGIC_MISC.all;
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ENTITY hue IS
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PORT
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(
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clk : in std_logic;
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reset_n : in std_logic;
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hue : in std_logic_vector(3 downto 0);
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burst : in std_logic;
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blank : in std_logic;
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vpos_lsb : in std_logic;
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pal : in std_logic;
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colour_osc : in std_logic_vector(1 downto 0);
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colour_osc_phased : out std_logic_vector(1 downto 0)
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);
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END hue;
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ARCHITECTURE vhdl OF hue IS
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signal sin_phase : std_logic_vector(7 downto 0);
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--signal sin_phase_real :real;
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signal sin_on : std_logic;
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signal hue_adj : std_logic_vector(3 downto 0);
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signal hue_delay : std_logic_vector(3 downto 0);
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signal colour_shift : std_logic_vector(7 downto 0);
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signal base_shift : std_logic_vector(7 downto 0);
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signal colour_osc_delay_next : std_logic_vector(511 downto 0);
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signal colour_osc_delay_reg : std_logic_vector(511 downto 0);
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signal colour_osc_phased_next : std_logic_vector(1 downto 0);
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signal colour_osc_phased_reg : std_logic_vector(1 downto 0);
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BEGIN
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process(clk,reset_n)
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begin
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if (reset_n='0') then
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colour_osc_delay_reg <= (others=>'0');
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colour_osc_phased_reg <= "00";
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elsif (clk'event and clk='1') then
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colour_osc_delay_reg <= colour_osc_delay_next;
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colour_osc_phased_reg <= colour_osc_phased_next;
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end if;
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end process;
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-- next state
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process(colour_osc_delay_reg,colour_osc)
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begin
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colour_osc_delay_next(511 downto 0) <= colour_osc_delay_reg(509 downto 0)&colour_osc;
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end process;
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process(colour_osc_delay_reg,sin_phase,sin_on)
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variable idx : integer;
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begin
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idx := to_integer(unsigned(sin_phase))/2;
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colour_osc_phased_next <= colour_osc_delay_reg(idx+1 downto idx);
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end process;
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-- 4.43361875MHz - PAL carrier - i.e. 12.8 clock cycles per sin wave! so if we have 256 sine entries,+5*16/4 per cycle, +20 per cycle
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-- 3.579545MHz - NTSC carrier - i.e. 16 clock cycles per sin wave. so if we have 256 sine entries,+16 per cycle
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-- NTSC:hue1=same phase as colour carrier, each next has 24 degree shift (adjustable) ... 17.066/256? Will 17 do?
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-- PAL:hue1=same phase as colour burst, each next has 22.5 degree shift (adjustable). adjust phase each line. 135/225 degrees for burst/hue1... 16/256, nice!
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process(hue,hue_adj,vpos_lsb,burst,pal)
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variable hue_use : std_logic_vector(3 downto 0);
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begin
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hue_adj <= "0000";
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hue_use := hue;
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if (burst = '1') then
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hue_use := x"1";
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end if;
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if pal='1' then
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-- pal has some gaps...
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if (unsigned(hue_use)>6) then
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hue_adj <= "000"&pal;
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end if;
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if (unsigned(hue_use)>10) then
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hue_adj <= "00"&pal&"0";
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end if;
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if vpos_lsb='1' then
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hue_delay <= std_logic_vector(to_unsigned(0,4)-unsigned(hue_use)-unsigned(hue_adj));
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else
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hue_delay <= std_logic_vector(to_unsigned(2,4)+unsigned(hue_use)+unsigned(hue_adj));
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end if;
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else
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hue_delay <= std_logic_vector(to_unsigned(0,4)-unsigned(hue_use));
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end if;
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end process;
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process(hue_delay,pal)
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begin
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colour_shift <= hue_delay&"0000";
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if pal='0' then
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colour_shift <= std_logic_vector(unsigned(hue_delay&"0000") + unsigned("000"&hue_delay&"0"));
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end if;
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end process;
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process(pal)
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begin
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if (pal = '1') then
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base_shift <= std_logic_vector(to_unsigned(112,8)); -- 157.5 degrees (256*157.5/360)
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else
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base_shift <= std_logic_vector(to_unsigned(248,8)); -- -12 degrees (256*348/360)
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end if;
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end process;
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process(blank,burst,colour_shift,hue,sin_phase,base_shift)
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begin
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sin_on <= '0';
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sin_phase <=std_logic_vector(unsigned(base_shift)+unsigned(colour_shift));
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--sin_phase_real <= real(to_integer(unsigned(sin_phase)))*real(360)/real(256);
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if (blank='1') then
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sin_on <= burst;
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else
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sin_on <= or_reduce(hue);
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end if;
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end process;
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colour_osc_phased <= colour_osc_phased_reg when sin_on='1' else "00";
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END vhdl;
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