repo2/unmerged/core/mist/internalromram.vhd
| 1 | markw | LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_unsigned.all;
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ENTITY internalromram IS
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PORT(
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clock : IN STD_LOGIC; --system clock
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reset_n : IN STD_LOGIC; --asynchronous reset
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ROM_ADDR : in STD_LOGIC_VECTOR(21 downto 0);
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ROM_REQUEST_COMPLETE : out STD_LOGIC;
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ROM_REQUEST : in std_logic;
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ROM_DATA : out std_logic_vector(7 downto 0);
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RAM_ADDR : in STD_LOGIC_VECTOR(18 downto 0);
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RAM_WR_ENABLE : in std_logic;
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RAM_DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
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RAM_REQUEST_COMPLETE : out STD_LOGIC;
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RAM_REQUEST : in std_logic;
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RAM_DATA : out std_logic_vector(7 downto 0)
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);
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END internalromram;
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architecture vhdl of internalromram is
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component ramint IS
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PORT
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(
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address : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
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clock : IN STD_LOGIC := '1';
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data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
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wren : IN STD_LOGIC ;
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q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
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);
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END component;
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component rom16 IS
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PORT
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(
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address : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
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clock : IN STD_LOGIC := '1';
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q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
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);
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END component;
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component basic IS
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PORT
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(
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address : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
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clock : IN STD_LOGIC := '1';
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q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
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);
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END component;
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signal rom_request_reg : std_logic;
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signal ram_request_reg : std_logic;
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signal ROM16_DATA : std_logic_vector(7 downto 0);
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signal BASIC_DATA : std_logic_vector(7 downto 0);
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signal RAM_WR_ENABLE_REAL : std_logic;
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signal IRAM_DATA : std_logic_vector(7 downto 0);
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begin
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process(clock,reset_n)
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begin
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if (reset_n ='0') then
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rom_request_reg <= '0';
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ram_request_reg <= '0';
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elsif (clock'event and clock='1') then
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rom_request_reg <= rom_request;
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ram_request_reg <= ram_request;
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end if;
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end process;
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rom_request_complete <= rom_request_reg;
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--C000 = basic.
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--0000-07FF = low
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--0800-27ff high
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process(rom16_data,basic_data, rom_addr(15 downto 0))
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begin
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ROM_DATA <= ROM16_DATA;
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if (rom_addr(15)='1') then
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ROM_DATA <= BASIC_DATA;
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end if;
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end process;
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--ROM_DATA <= ROMLO_DATA when rom_addr(15 downto 12)=X"D" else ROMHI_DATA;
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--ROM_DATA <= ROMHI_DATA;
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-- basic1 : basic
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-- PORT MAP(clock => clock,
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-- address => rom_addr(12 downto 0),
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-- q => BASIC_data
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-- );
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--
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-- rom16a : rom16
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-- PORT MAP(clock => clock,
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-- address => rom_addr(13 downto 0),
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-- q => ROM16_data
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-- );
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--
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-- ramint1 : ramint
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-- PORT MAP(clock => clock,
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-- address => ram_addr(12 downto 0),
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-- data => ram_data_in(7 downto 0),
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-- wren => RAM_WR_ENABLE_REAL,
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-- q => iram_data
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-- );
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ram_request_complete <= ram_request_reg;
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RAM_DATA <= IRAM_DATA when ram_addr(15 downto 13)= "000" else X"FF";
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RAM_WR_ENABLE_REAL <= RAM_WR_ENABLE when ram_addr(15 downto 13)="000" else '0'; -- ban writes over 8k when using int ram - HACK
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end vhdl;
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