repo2/ultimate_cart/veronica/veronica_address_decoder.vhd
| 438 | markw | LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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use IEEE.STD_LOGIC_MISC.all;
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ENTITY veronica_address_decoder IS
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PORT (
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addr_in: in std_logic_vector(15 downto 0);
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window_address : in std_logic;
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bank_half_select : in std_logic;
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bank_select : in std_logic;
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config_select : out std_logic;
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sram_select : out std_logic;
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sram_address : out std_logic_vector(16 downto 0)
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);
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END veronica_address_decoder;
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ARCHITECTURE vhdl OF veronica_address_decoder IS
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signal bank_access : std_logic;
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signal config_select_int : std_logic;
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begin
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-- window_address 0=0xc0000->0xffff, 1=0x4000->0x7fff
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-- config_address 0x200->0x20f
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bank_access <= (window_address xor addr_in(15)) and addr_in(14);
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process(bank_access,bank_select,bank_half_select,addr_in)
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begin
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sram_address <= '0'&addr_in;
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if (bank_access='1') then
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sram_address(16 downto 14) <= '1'¬(bank_select)&bank_half_select;
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end if;
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end process;
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config_select_int <= not(or_reduce(addr_in(15 downto 10)&addr_in(8 downto 4))) and addr_in(9);
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config_select <= config_select_int;
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sram_select <= not(config_select_int);
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end vhdl;
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