repo2/ultimate_cart/veronica/tb_veronica/veronica_tb.vhd
| 451 | markw | library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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library std_developerskit ; -- used for to_string
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-- use std_developerskit.std_iopak.all;
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entity veronica_tb is
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end;
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architecture rtl of veronica_tb is
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constant CLK_PERIOD : time := 1 us / (40);
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constant CLK_CART_PERIOD : time := 1 us / (1.79*32);
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signal reset_n : std_logic;
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signal clk : std_logic;
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signal clk_cart : std_logic;
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signal EXT_SRAM_ADDR: std_logic_vector(19 downto 0);
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signal EXT_SRAM_DATA: std_logic_vector(7 downto 0);
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signal EXT_SRAM_CE: std_logic;
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signal EXT_SRAM_OE: std_logic;
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signal EXT_SRAM_WE: std_logic;
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signal CART_ADDR: std_logic_vector(12 downto 0);
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signal CART_DATA: std_logic_vector(7 downto 0);
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signal CART_RD5: std_logic;
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signal CART_RD4: std_logic;
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signal CART_S5: std_logic;
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signal CART_S4: std_logic;
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signal CART_PHI2: std_logic;
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signal CART_CTL: std_logic;
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signal CART_RW: std_logic;
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signal LED : std_logic_vector(0 downto 0);
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signal SD_CARD_cs: std_logic;
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signal SD_CARD_sclk: std_logic;
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signal SD_CARD_mosi: std_logic;
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signal SD_CARD_miso: std_logic;
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-- 6502 bus other side
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signal enable_179_early : std_logic;
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signal cart_request : std_logic;
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signal pbi_addr_out : std_logic_vector(15 downto 0);
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signal cart_data_write : std_logic_vector(7 downto 0);
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signal pbi_write_enable : std_logic;
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signal s4_n : std_logic;
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signal s5_n : std_logic;
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signal cctl_n : std_logic;
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signal cart_data_read : std_logic_vector(7 downto 0);
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signal cart_complete : std_logic;
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signal bus_data_in : std_logic_vector(7 downto 0);
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signal bus_data_out : std_logic_vector(7 downto 0);
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signal bus_data_oe : std_logic;
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signal bus_addr_out : std_logic_vector(15 downto 0);
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signal bus_addr_oe : std_logic;
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signal bus_write_n : std_logic;
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signal bus_s4_n : std_logic;
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signal bus_s5_n : std_logic;
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signal bus_cctl_n : std_logic;
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signal bus_control_oe : std_logic;
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begin
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p_clk_gen_a : process
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begin
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clk <= '1';
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wait for CLK_PERIOD/2;
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clk <= '0';
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wait for CLK_PERIOD - (CLK_PERIOD/2 );
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end process;
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p_clk_gen_b : process
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begin
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clk_cart <= '1';
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wait for CLK_CART_PERIOD/2;
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clk_cart <= '0';
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wait for CLK_CART_PERIOD - (CLK_CART_PERIOD/2 );
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end process;
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reset_n <= '0', '1' after 1000ns;
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process_enable : process
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begin
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '1'; -- HERE!
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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end process;
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process_setup_sram : process
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begin
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cart_request <= '0';
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pbi_addr_out <= (others=>'0');
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cart_data_write <= (others=>'0');
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pbi_write_enable <= '0';
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s4_n <= '1';
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s5_n <= '1';
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cctl_n <= '1';
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wait for 3000ns;
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wait until enable_179_early'event and enable_179_early = '1';
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cart_request <= '1';
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pbi_addr_out <= x"D5C1";
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cart_data_write <= x"ec";
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pbi_write_enable <= '1';
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cctl_n <= '0';
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wait until enable_179_early'event and enable_179_early = '1';
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cart_request <= '1';
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pbi_write_enable <= '0';
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wait until enable_179_early'event and enable_179_early = '1';
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pbi_addr_out <= x"D5c0";
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wait until enable_179_early'event and enable_179_early = '1';
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--cart_data_write <= x"ec";
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cart_data_write <= x"ed";
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pbi_write_enable <= '1';
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wait until enable_179_early'event and enable_179_early = '1';
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pbi_write_enable <= '0';
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wait until enable_179_early'event and enable_179_early = '1';
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cart_request <= '0';
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cctl_n <= '1';
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wait for 100000000us;
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end process;
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thebigone: entity work.veronica
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port map
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(
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CLK => clk,
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LED => LED,
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CART_ADDR => CART_ADDR,
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CART_DATA => CART_DATA,
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CART_RD5 => CART_RD5,
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CART_RD4 => CART_RD4,
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CART_S5 => CART_S5,
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CART_S4 => CART_S4,
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CART_PHI2 => CART_PHI2,
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CART_CTL => CART_CTL,
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CART_RW => CART_RW,
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SD_CARD_cs => SD_CARD_cs,
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SD_CARD_sclk => SD_CARD_sclk,
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SD_CARD_mosi => SD_CARD_mosi,
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SD_CARD_miso => SD_CARD_miso,
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EXT_SRAM_ADDR => EXT_SRAM_ADDR,
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EXT_SRAM_DATA => EXT_SRAM_DATA,
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EXT_SRAM_CE => EXT_SRAM_CE,
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EXT_SRAM_OE => EXT_SRAM_OE,
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EXT_SRAM_WE => EXT_SRAM_WE
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);
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bus_adaptor : ENTITY work.timing6502
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GENERIC MAP
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(
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CYCLE_LENGTH => 32,
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CONTROl_BITS => 3
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)
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PORT MAP
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(
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CLK => clk_cart,
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RESET_N => reset_n,
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-- FPGA side
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ENABLE_179_EARLY =>enable_179_early,
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REQUEST => cart_request,
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ADDR_IN => pbi_addr_out,
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DATA_IN => cart_data_write,
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WRITE_IN => pbi_write_enable,
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CONTROL_N_IN => s4_n&s5_n&cctl_n,
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DATA_OUT => cart_data_read,
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COMPLETE => cart_complete,
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-- 6502 side
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BUS_DATA_IN => CART_DATA,
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BUS_PHI1 => open,
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BUS_PHI2 => CART_PHI2,
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BUS_SUBCYCLE => open,
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BUS_ADDR_OUT => bus_addr_out,
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BUS_ADDR_OE => bus_addr_oe,
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BUS_DATA_OUT => bus_data_out,
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BUS_DATA_OE => bus_data_oe,
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BUS_WRITE_N => CART_RW,
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BUS_CONTROL_N(2) => bus_s4_n,
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BUS_CONTROL_N(1) => bus_s5_n,
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BUS_CONTROL_N(0) => bus_cctl_n,
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BUS_CONTROL_OE => bus_control_oe
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);
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CART_ADDR <= bus_addr_out(12 downto 0) when bus_addr_oe='1' else (others=>'Z');
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CART_DATA <= bus_data_out when bus_data_oe='1' else (others=>'Z');
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CART_S4 <= bus_s4_n when bus_control_oe='1' else 'Z';
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CART_S5 <= bus_s5_n when bus_control_oe='1' else 'Z';
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CART_CTL <= bus_cctl_n when bus_control_oe='1' else 'Z';
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| 453 | markw | sram_model : entity work.sram
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generic map
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(
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clear_on_power_up => TRUE,
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-- Clearing of RAM is carried out before download takes place
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download_on_power_up => FALSE, -- if TRUE, RAM is downloaded at start of simulation
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trace_ram_load => TRUE, -- Echoes the data downloaded to the RAM on the screen
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-- (included for debugging purposes)
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enable_nWE_only_control => TRUE, -- Read-/write access controlled by nWE only
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-- nOE may be kept active all the time
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-- Configuring RAM size
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size => 131072, -- number of memory words
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adr_width => 17, -- number of address bits
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width => 8, -- number of bits per memory word
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-- READ-cycle timing parameters
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tAA_max => 55 NS, -- Address Access Time
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tOHA_min => 3 NS, -- Output Hold Time
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tACE_max => 55 NS, -- nCE/CE2 Access Time
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tDOE_max => 30 NS, -- nOE Access Time
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tLZOE_min=> 5 NS, -- nOE to Low-Z Output
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tHZOE_max=> 20 NS, -- OE to High-Z Output
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tLZCE_min=> 10 NS, -- nCE/CE2 to Low-Z Output
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tHZCE_max=> 20 NS, -- CE/nCE2 to High Z Output
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-- WRITE-cycle timing parameters
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tWC_min => 55 NS, -- Write Cycle Time
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tSCE_min=> 50 NS, -- nCE/CE2 to Write End
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tAW_min => 50 NS, -- tAW Address Set-up Time to Write End
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tHA_min => 0 NS, -- tHA Address Hold from Write End
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tSA_min => 0 NS, -- Address Set-up Time
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tPWE_min=> 45 NS, -- nWE Pulse Width
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tSD_min => 25 NS, -- Data Set-up to Write End
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tHD_min => 0 NS, -- Data Hold from Write End
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tHZWE_max=> 20 NS, -- nWE Low to High-Z Output
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tLZWE_min=> 0 NS -- nWE High to Low-Z Output
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)
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--signal EXT_SRAM_ADDR: std_logic_vector(19 downto 0);
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--signal EXT_SRAM_DATA: std_logic_vector(7 downto 0);
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--signal EXT_SRAM_CE: std_logic;
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--signal EXT_SRAM_OE: std_logic;
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--signal EXT_SRAM_WE: std_logic;
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port map
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(
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nCE => EXT_SRAM_CE,
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nOE => EXT_SRAM_OE,
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nWE => EXT_SRAM_WE,
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A => EXT_SRAM_ADDR(16 downto 0),
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D => EXT_SRAM_DATA
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);
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| 451 | markw | ||
end rtl;
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