repo2/ultimate_cart/veronica/tb_veronica/pll_veronica.vhd
| 451 | markw | LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY pll_veronica IS
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PORT
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(
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inclk0 : IN STD_LOGIC;
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c0 : OUT STD_LOGIC;
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c1 : OUT STD_LOGIC;
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locked : OUT STD_LOGIC
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);
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END pll_veronica;
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ARCHITECTURE vhdl OF pll_veronica IS
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constant CLK0_PERIOD : time := 1 us / (14);
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constant CLK1_PERIOD : time := 1 us / (14*7);
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begin
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p_clk_gen_a : process
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begin
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c0 <= '1';
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wait for CLK0_PERIOD/2;
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c0 <= '0';
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wait for CLK0_PERIOD - (CLK0_PERIOD/2 );
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end process;
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p_clk_gen_b : process
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begin
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c1 <= '1';
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wait for CLK1_PERIOD/2;
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c1 <= '0';
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wait for CLK1_PERIOD - (CLK1_PERIOD/2 );
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end process;
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locked <= '0', '1' after 2000ns;
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end vhdl;
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