repo2/ultimate_cart/veronica/load_mac.v
| 438 | markw | // ============================================================================
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// __
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// \\__/ o\ (C) 2014 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@opencores.org
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// ||
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
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LOAD_MAC1:
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`ifdef SUPPORT_DCACHE
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if (unCachedData)
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`endif
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begin
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if (isRMW)
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mlb <= 1'b1;
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if (isBrk)
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vpb <= `TRUE;
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data_read(radr);
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state <= LOAD_MAC2;
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end
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`ifdef SUPPORT_DCACHE
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else if (dhit)
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load_tsk(rdat,rdat8,rdat16);
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else begin
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retstate <= LOAD_MAC1;
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state <= DCACHE1;
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end
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`endif
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LOAD_MAC2:
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if (rdy) begin
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data_nack();
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| 685 | markw | `include "load_tsk.v"
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// load_tsk(db,b16);
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| 438 | markw | end
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`ifdef SUPPORT_BERR
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else if (err_i) begin
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mlb <= 1'b0;
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data_nack();
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derr_address <= ado;
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intno <= 9'd508;
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state <= BUS_ERROR;
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end
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`endif
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RTS1:
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begin
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vpa <= `TRUE;
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vda <= `TRUE;
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pc <= pc + 24'd1;
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ado <= pc + 24'd1;
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next_state(IFETCH1);
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end
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BYTE_IX5:
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begin
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isI24 <= `FALSE;
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radr <= ia;
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load_what <= m16 ? `HALF_70 : `BYTE_70;
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state <= LOAD_MAC1;
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if (ir[7:0]==`STA_IX || ir[7:0]==`STA_I || ir[7:0]==`STA_IL) begin
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wadr <= ia;
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store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
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state <= STORE1;
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end
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else if (ir[7:0]==`PEI) begin
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set_sp();
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store_what <= `STW_IA158;
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state <= STORE1;
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end
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end
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BYTE_IY5:
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begin
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isIY <= `FALSE;
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isIY24 <= `FALSE;
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radr <= iapy8;
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wadr <= iapy8;
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store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
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load_what <= m16 ? `HALF_70 : `BYTE_70;
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$display("IY addr: %h", iapy8);
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if (ir[7:0]==`STA_IY || ir[7:0]==`STA_IYL || ir[7:0]==`STA_DSPIY)
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state <= STORE1;
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else
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state <= LOAD_MAC1;
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end
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