repo2/sockit/avalon_arm_regs.vhdl
| 311 | markw | ---------------------------------------------------------------------------
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-- (c) 2014 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY avalon_arm_regs IS
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GENERIC
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(
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platform : integer := 1 -- So ROM can detect which type of system...
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);
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PORT
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(
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CLK : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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POKEY_ENABLE : in std_logic;
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-- avalon signals
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CHIPSELECT : IN STD_LOGIC;
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ADDRESS : IN STD_LOGIC_VECTOR(10 downto 0);
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READ: IN STD_LOGIC;
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READDATA : OUT STD_LOGIC_VECTOR(31 downto 0);
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WRITE : IN STD_LOGIC;
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WRITEDATA : IN STD_LOGIC_VECTOR(31 downto 0);
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BYTEENABLE : IN STD_LOGIC_VECTOR(3 downto 0);
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-- GENERIC INPUT REGS (need to synchronize upstream...)
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IN1 : in std_logic_vector(31 downto 0);
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IN2 : in std_logic_vector(31 downto 0);
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IN3 : in std_logic_vector(31 downto 0);
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IN4 : in std_logic_vector(31 downto 0);
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-- GENERIC OUTPUT REGS
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OUT1 : out std_logic_vector(31 downto 0);
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OUT2 : out std_logic_vector(31 downto 0);
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OUT3 : out std_logic_vector(31 downto 0);
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OUT4 : out std_logic_vector(31 downto 0);
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OUT5 : out std_logic_vector(31 downto 0);
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OUT6 : out std_logic_vector(31 downto 0);
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-- ATARI interface (in future we can also turbo load by directly hitting memory...)
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SIO_DATA_IN : out std_logic;
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SIO_COMMAND : in std_logic;
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SIO_DATA_OUT : in std_logic
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);
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END avalon_arm_regs;
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ARCHITECTURE vhdl OF avalon_arm_regs IS
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function vectorize(s: std_logic) return std_logic_vector is
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variable v: std_logic_vector(0 downto 0);
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begin
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v(0) := s;
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return v;
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end;
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signal device_decoded : std_logic_vector(7 downto 0);
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signal device_wr_en : std_logic_vector(7 downto 0);
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signal device_rd_en : std_logic_vector(7 downto 0);
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signal addr_decoded : std_logic_vector(15 downto 0);
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signal out1_next : std_logic_vector(31 downto 0);
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signal out1_reg : std_logic_vector(31 downto 0);
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signal out2_next : std_logic_vector(31 downto 0);
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signal out2_reg : std_logic_vector(31 downto 0);
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signal out3_next : std_logic_vector(31 downto 0);
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signal out3_reg : std_logic_vector(31 downto 0);
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signal out4_next : std_logic_vector(31 downto 0);
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signal out4_reg : std_logic_vector(31 downto 0);
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signal out5_next : std_logic_vector(31 downto 0);
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signal out5_reg : std_logic_vector(31 downto 0);
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signal out6_next : std_logic_vector(31 downto 0);
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signal out6_reg : std_logic_vector(31 downto 0);
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signal pokey_data_out : std_logic_vector(7 downto 0);
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signal subtimer_next : std_logic_vector(10 downto 0);
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signal subtimer_reg : std_logic_vector(10 downto 0);
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signal timer_next : std_logic_vector(31 downto 0);
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signal timer_reg : std_logic_vector(31 downto 0);
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signal data_out_regs : std_logic_vector(31 downto 0);
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signal data_out_mux : std_logic_vector(31 downto 0);
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signal read_sel : std_logic;
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signal write_sel : std_logic;
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begin
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-- register
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process(clk,reset_n)
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begin
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if (reset_n='0') then
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out1_reg <= (others=>'0');
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out2_reg <= (others=>'0');
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out3_reg <= (others=>'0');
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out4_reg <= (others=>'0');
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out5_reg <= (others=>'0');
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out6_reg <= (others=>'0');
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subtimer_reg <= (others=>'0');
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timer_reg <= (others=>'0');
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elsif (clk'event and clk='1') then
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out1_reg <= out1_next;
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out2_reg <= out2_next;
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out3_reg <= out3_next;
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out4_reg <= out4_next;
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out5_reg <= out5_next;
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out6_reg <= out6_next;
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subtimer_reg <= subtimer_next;
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timer_reg <= timer_next;
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end if;
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end process;
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-- decode address
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decode_addr : entity work.complete_address_decoder
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generic map(width=>4)
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port map (addr_in=>address(3 downto 0), addr_decoded=>addr_decoded);
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decode_device : entity work.complete_address_decoder
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generic map(width=>3)
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port map (addr_in=>address(10 downto 8), addr_decoded=>device_decoded);
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-- device decode
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-- 0x000 - own regs (0)
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-- 0x100 - pokey (1)
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write_sel <= write and chipselect;
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read_sel <= read and chipselect;
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device_wr_en <= device_decoded and (write_sel&write_sel&write_sel&write_sel&write_sel&write_sel&write_sel&write_sel);
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device_rd_en <= device_decoded and (read_sel&read_sel&read_sel&read_sel&read_sel&read_sel&read_sel&read_sel);
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-- uart - another Pokey! Running at atari frequency.
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-- with a state machine to capture command packets
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-- can not easily poll frequently enough with zpu when also polling usb
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-- pokey1 : entity work.pokey
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-- port map (clk=>clk,ENABLE_179=>pokey_enable,addr=>addr(3 downto 0),data_in=>WRITEDATA(7 downto 0),wr_en=>device_wr_en(1),
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-- reset_n=>reset_n,keyboard_response=>"11",pot_in=>X"00",
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-- sio_in1=>sio_data_out,sio_in2=>'1',sio_in3=>'1', -- TODO, pokey dir...
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-- data_out=>pokey_data_out,
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-- sio_out1=>sio_data_in);
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pokey1 : entity work.sio_device
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PORT MAP
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(
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CLK => CLK,
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ADDR => address(4 downto 0),
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CPU_DATA_IN => WRITEDATA(7 downto 0),
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EN => device_rd_en(1),
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WR_EN => device_wr_en(1),
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RESET_N => reset_n,
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POKEY_ENABLE => pokey_enable,
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SIO_DATA_IN => sio_data_in,
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SIO_COMMAND => sio_command,
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SIO_DATA_OUT => sio_data_out,
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-- CPU interface
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DATA_OUT => pokey_data_out
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);
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-- timer for approx ms
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process(timer_reg,subtimer_reg, pokey_enable)
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begin
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timer_next <= timer_reg;
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subtimer_next <= subtimer_reg;
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if (pokey_enable = '1') then
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subtimer_next <= std_logic_vector(unsigned(subtimer_reg)-1);
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end if;
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if (subtimer_reg = "000"&x"00") then
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subtimer_next <= std_logic_vector(to_unsigned(11#1790#,11));
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timer_next <= std_logic_vector(unsigned(timer_reg)+1);
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end if;
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end process;
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process(device_decoded, data_out_regs, pokey_data_out)
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begin
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data_out_mux <= (others=>'0');
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if (device_decoded(0) = '1') then
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data_out_mux <= data_out_regs;
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end if;
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if (device_decoded(1) = '1') then
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data_out_mux(7 downto 0) <= pokey_data_out;
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end if;
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end process;
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-- hardware regs for ZPU
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--
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-- 0-3: GENERIC INPUT (RO)
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-- 4-7: GENERIC OUTPUT (R/W)
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-- 8: W:PAUSE, R:Timer (1ms)
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-- 9: SPI_DATA
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-- SPI_DATA (DONE)
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-- W - write data (starts transmission)
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-- R - read data (wait for complete first)
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-- 10: SPI_STATE
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-- SPI_STATE/SPI_CTRL (DONE)
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-- R: 0=busy
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-- W: 0=select_n, speed
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-- 11: SIO
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-- SIO
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-- R: 0=CMD
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-- 12: TYPE
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-- FPGA board (DONE)
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-- R(32 bits) 0=DE1
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-- 13 : SPI_DMA
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-- W(15 downto 0 = addr),(31 downto 16 = endAddr)
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-- 14-15 : GENERIC OUTPUT (R/W)
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-- 16-31: POKEY! Low bytes only... i.e. pokey reg every 4 bytes...
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-- Writes to registers
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process(WRITEDATA,device_wr_en,address,addr_decoded, out1_reg, out2_reg, out3_reg, out4_reg, out5_reg, out6_reg, pokey_enable)
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begin
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out1_next <= out1_reg;
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out2_next <= out2_reg;
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out3_next <= out3_reg;
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out4_next <= out4_reg;
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out5_next <= out5_reg;
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out6_next <= out6_reg;
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if (device_wr_en(0) = '1') then
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if(addr_decoded(4) = '1') then
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out1_next <= WRITEDATA;
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end if;
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if(addr_decoded(5) = '1') then
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out2_next <= WRITEDATA;
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end if;
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if(addr_decoded(6) = '1') then
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out3_next <= WRITEDATA;
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end if;
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if(addr_decoded(7) = '1') then
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out4_next <= WRITEDATA;
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end if;
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if(addr_decoded(14) = '1') then
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out5_next <= WRITEDATA;
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end if;
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if(addr_decoded(15) = '1') then
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out6_next <= WRITEDATA;
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end if;
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end if;
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end process;
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-- Read from registers
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process(address,addr_decoded, in1, in2, in3, in4, out1_reg, out2_reg, out3_reg, out4_reg, out5_reg, out6_reg, SIO_COMMAND, timer_reg)
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begin
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data_out_regs <= (others=>'0');
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if (addr_decoded(0) = '1') then
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data_out_regs <= in1;
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end if;
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if (addr_decoded(1) = '1') then
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data_out_regs <= in2;
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end if;
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if (addr_decoded(2) = '1') then
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data_out_regs <= in3;
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end if;
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if (addr_decoded(3) = '1') then
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data_out_regs <= in4;
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end if;
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if (addr_decoded(4) = '1') then
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data_out_regs <= out1_reg;
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end if;
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if (addr_decoded(5) = '1') then
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data_out_regs <= out2_reg;
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end if;
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if (addr_decoded(6) = '1') then
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data_out_regs <= out3_reg;
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end if;
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if (addr_decoded(7) = '1') then
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data_out_regs <= out4_reg;
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end if;
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if (addr_decoded(14) = '1') then
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data_out_regs <= out5_reg;
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end if;
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if (addr_decoded(15) = '1') then
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data_out_regs <= out6_reg;
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end if;
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if (addr_decoded(8) = '1') then
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data_out_regs <= timer_reg;
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end if;
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if(addr_decoded(11) = '1') then
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data_out_regs(0) <= SIO_COMMAND;
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end if;
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if (addr_decoded(12) = '1') then
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data_out_regs <= std_logic_vector(to_unsigned(platform,32));
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end if;
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end process;
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-- outputs
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out1 <= out1_reg;
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out2 <= out2_reg;
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out3 <= out3_reg;
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out4 <= out4_reg;
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out5 <= out5_reg;
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out6 <= out6_reg;
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READDATA <= data_out_mux;
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end vhdl;
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