repo2/sockit/altiobufo.vhd
| 302 | markw | -- megafunction wizard: %ALTIOBUF%
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-- GENERATION: STANDARD
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-- VERSION: WM1.0
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-- MODULE: altiobuf_out
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-- ============================================================
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-- File Name: altiobufo.vhd
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-- Megafunction Name(s):
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-- altiobuf_out
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--
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-- Simulation Library Files(s):
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-- cyclonev
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-- ============================================================
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-- ************************************************************
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-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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--
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-- 14.0.0 Build 200 06/17/2014 SJ Web Edition
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-- ************************************************************
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--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
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--Your use of Altera Corporation's design tools, logic functions
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--and other software and tools, and its AMPP partner logic
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--functions, and any output files from any of the foregoing
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--(including device programming or simulation files), and any
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--associated documentation or information are expressly subject
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--to the terms and conditions of the Altera Program License
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--Subscription Agreement, the Altera Quartus II License Agreement,
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--the Altera MegaCore Function License Agreement, or other
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--applicable license agreement, including, without limitation,
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--that your use is for the sole purpose of programming logic
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--devices manufactured by Altera and sold by Altera or its
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--authorized distributors. Please refer to the applicable
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--agreement for further details.
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--altiobuf_out CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" LEFT_SHIFT_SERIES_TERMINATION_CONTROL="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="TRUE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b oe oe_b
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--VERSION_BEGIN 14.0 cbx_altiobuf_out 2014:06:05:09:45:41:SJ cbx_mgl 2014:06:05:10:17:12:SJ cbx_stratixiii 2014:06:05:09:45:41:SJ cbx_stratixv 2014:06:05:09:45:41:SJ VERSION_END
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LIBRARY cyclonev;
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USE cyclonev.all;
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--synthesis_resources = cyclonev_io_obuf 2 cyclonev_pseudo_diff_out 1
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY altiobufo_iobuf_out_h5u IS
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PORT
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(
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datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
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dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
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dataout_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
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oe : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '1');
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oe_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '1')
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);
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END altiobufo_iobuf_out_h5u;
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ARCHITECTURE RTL OF altiobufo_iobuf_out_h5u IS
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SIGNAL wire_obuf_ba_o : STD_LOGIC;
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SIGNAL wire_obuf_ba_oe : STD_LOGIC_VECTOR (0 DOWNTO 0);
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SIGNAL wire_pseudo_diffa_w_lg_oebout3w : STD_LOGIC_VECTOR (0 DOWNTO 0);
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SIGNAL wire_obufa_o : STD_LOGIC;
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SIGNAL wire_obufa_oe : STD_LOGIC_VECTOR (0 DOWNTO 0);
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SIGNAL wire_pseudo_diffa_w_lg_oeout2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
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SIGNAL wire_pseudo_diffa_o : STD_LOGIC;
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SIGNAL wire_pseudo_diffa_obar : STD_LOGIC;
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SIGNAL wire_pseudo_diffa_oebout : STD_LOGIC;
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SIGNAL wire_pseudo_diffa_oein : STD_LOGIC_VECTOR (0 DOWNTO 0);
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SIGNAL wire_w_lg_oe_w1w : STD_LOGIC_VECTOR (0 DOWNTO 0);
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SIGNAL wire_pseudo_diffa_oeout : STD_LOGIC;
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SIGNAL oe_w : STD_LOGIC_VECTOR (0 DOWNTO 0);
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COMPONENT cyclonev_io_obuf
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GENERIC
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(
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bus_hold : STRING := "false";
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open_drain_output : STRING := "false";
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shift_series_termination_control : STRING := "false";
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lpm_type : STRING := "cyclonev_io_obuf"
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);
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PORT
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(
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dynamicterminationcontrol : IN STD_LOGIC := '0';
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i : IN STD_LOGIC := '0';
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o : OUT STD_LOGIC;
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obar : OUT STD_LOGIC;
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oe : IN STD_LOGIC := '1';
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parallelterminationcontrol : IN STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
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seriesterminationcontrol : IN STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0')
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);
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END COMPONENT;
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COMPONENT cyclonev_pseudo_diff_out
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PORT
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(
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dtc : OUT STD_LOGIC;
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dtcbar : OUT STD_LOGIC;
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dtcin : IN STD_LOGIC := '0';
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i : IN STD_LOGIC := '0';
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o : OUT STD_LOGIC;
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obar : OUT STD_LOGIC;
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oebout : OUT STD_LOGIC;
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oein : IN STD_LOGIC := '0';
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oeout : OUT STD_LOGIC
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);
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END COMPONENT;
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BEGIN
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dataout(0) <= wire_obufa_o;
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dataout_b(0) <= wire_obuf_ba_o;
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oe_w <= oe;
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wire_obuf_ba_oe <= wire_pseudo_diffa_w_lg_oebout3w;
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wire_pseudo_diffa_w_lg_oebout3w(0) <= NOT wire_pseudo_diffa_oebout;
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obuf_ba : cyclonev_io_obuf
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GENERIC MAP (
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bus_hold => "false",
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open_drain_output => "false"
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)
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PORT MAP (
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i => wire_pseudo_diffa_obar,
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o => wire_obuf_ba_o,
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oe => wire_obuf_ba_oe(0)
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);
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wire_obufa_oe <= wire_pseudo_diffa_w_lg_oeout2w;
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wire_pseudo_diffa_w_lg_oeout2w(0) <= NOT wire_pseudo_diffa_oeout;
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obufa : cyclonev_io_obuf
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GENERIC MAP (
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bus_hold => "false",
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open_drain_output => "false"
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)
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PORT MAP (
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i => wire_pseudo_diffa_o,
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o => wire_obufa_o,
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oe => wire_obufa_oe(0)
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);
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wire_pseudo_diffa_oein <= wire_w_lg_oe_w1w;
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wire_w_lg_oe_w1w(0) <= NOT oe_w(0);
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pseudo_diffa : cyclonev_pseudo_diff_out
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PORT MAP (
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i => datain(0),
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o => wire_pseudo_diffa_o,
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obar => wire_pseudo_diffa_obar,
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oebout => wire_pseudo_diffa_oebout,
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oein => wire_pseudo_diffa_oein(0),
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oeout => wire_pseudo_diffa_oeout
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);
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END RTL; --altiobufo_iobuf_out_h5u
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--VALID FILE
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY altiobufo IS
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PORT
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(
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datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
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oe : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
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oe_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
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dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
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dataout_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
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);
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END altiobufo;
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ARCHITECTURE RTL OF altiobufo IS
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SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
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SIGNAL sub_wire1 : STD_LOGIC_VECTOR (0 DOWNTO 0);
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COMPONENT altiobufo_iobuf_out_h5u
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PORT (
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datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
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oe : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
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oe_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
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dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
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dataout_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
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);
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END COMPONENT;
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BEGIN
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dataout <= sub_wire0(0 DOWNTO 0);
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dataout_b <= sub_wire1(0 DOWNTO 0);
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altiobufo_iobuf_out_h5u_component : altiobufo_iobuf_out_h5u
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PORT MAP (
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datain => datain,
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oe => oe,
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oe_b => oe_b,
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dataout => sub_wire0,
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dataout_b => sub_wire1
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);
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END RTL;
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-- ============================================================
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-- CNX file retrieval info
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-- ============================================================
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-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
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-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
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-- Retrieval info: CONSTANT: enable_bus_hold STRING "FALSE"
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-- Retrieval info: CONSTANT: left_shift_series_termination_control STRING "FALSE"
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-- Retrieval info: CONSTANT: number_of_channels NUMERIC "1"
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-- Retrieval info: CONSTANT: open_drain_output STRING "FALSE"
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-- Retrieval info: CONSTANT: pseudo_differential_mode STRING "TRUE"
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-- Retrieval info: CONSTANT: use_differential_mode STRING "TRUE"
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-- Retrieval info: CONSTANT: use_oe STRING "TRUE"
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-- Retrieval info: CONSTANT: use_termination_control STRING "FALSE"
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-- Retrieval info: USED_PORT: datain 0 0 1 0 INPUT NODEFVAL "datain[0..0]"
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-- Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
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-- Retrieval info: USED_PORT: dataout_b 0 0 1 0 OUTPUT NODEFVAL "dataout_b[0..0]"
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-- Retrieval info: USED_PORT: oe 0 0 1 0 INPUT NODEFVAL "oe[0..0]"
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-- Retrieval info: USED_PORT: oe_b 0 0 1 0 INPUT NODEFVAL "oe_b[0..0]"
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-- Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 1 0
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-- Retrieval info: CONNECT: @oe 0 0 1 0 oe 0 0 1 0
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-- Retrieval info: CONNECT: @oe_b 0 0 1 0 oe_b 0 0 1 0
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-- Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
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-- Retrieval info: CONNECT: dataout_b 0 0 1 0 @dataout_b 0 0 1 0
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobufo.vhd TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobufo.inc FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobufo.cmp TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobufo.bsf FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobufo_inst.vhd FALSE
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-- Retrieval info: LIB_FILE: cyclonev
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