EclaireXL

# file: planAhead_ise.tcl

#

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set projDir [file dirname [info script]]

set projName pll_pal

set topName pll_pal_exdes

set device xc6slx9tqg144-3

create_project $projName $projDir/results/$projName -part $device

set_property design_mode RTL [get_filesets sources_1]

## Source files

#set verilogSources [glob $srcDir/*.v]

import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/pll_pal_exdes.vhd

import_files -fileset [get_filesets sources_1] -force -norecurse ../../../pll_pal.vhd

#UCF file

import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/pll_pal_exdes.ucf

set_property top $topName [get_property srcset [current_run]]

launch_runs -runs synth_1

wait_on_run synth_1

set_property add_step Bitgen [get_runs impl_1]

launch_runs -runs impl_1

wait_on_run impl_1