repo2/papilioduo/pll/pll_pal/implement/implement.sh
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# file: implement.sh
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#
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# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
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#
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# This file contains confidential and proprietary information
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# of Xilinx, Inc. and is protected under U.S. and
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# international copyright and other intellectual property
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# laws.
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#
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# DISCLAIMER
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# This disclaimer is not a license and does not grant any
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# rights to the materials distributed herewith. Except as
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# otherwise provided in a valid license issued to you by
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# Xilinx, and to the maximum extent permitted by applicable
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# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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# (2) Xilinx shall not be liable (whether in contract or tort,
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# including negligence, or under any other theory of
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# liability) for any loss or damage of any kind or nature
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# related to, arising under or in connection with these
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# materials, including for any direct, or any indirect,
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# special, incidental, or consequential loss or damage
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# (including loss of data, profits, goodwill, or any type of
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# loss or damage suffered as a result of any action brought
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# by a third party) even if such damage or loss was
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# reasonably foreseeable or Xilinx had been advised of the
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# possibility of the same.
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#
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# CRITICAL APPLICATIONS
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# Xilinx products are not designed or intended to be fail-
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# safe, or for use in any application requiring fail-safe
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# performance, such as life-support or safety devices or
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# systems, Class III medical devices, nuclear facilities,
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# applications related to the deployment of airbags, or any
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# other applications that could lead to death, personal
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# injury, or severe property or environmental damage
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# (individually and collectively, "Critical
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# Applications"). Customer assumes the sole risk and
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# liability of any use of Xilinx products in Critical
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# Applications, subject only to applicable laws and
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# regulations governing limitations on product liability.
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#
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# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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# PART OF THIS FILE AT ALL TIMES.
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#
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#-----------------------------------------------------------------------------
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# Script to synthesize and implement the RTL provided for the clocking wizard
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#-----------------------------------------------------------------------------
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# Clean up the results directory
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rm -rf results
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mkdir results
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# Copy unisim_comp.v file to results directory
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cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/
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# Synthesize the Verilog Wrapper Files
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echo 'Synthesizing Clocking Wizard design with XST'
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xst -ifn xst.scr
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mv pll_pal_exdes.ngc results/
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# Copy the constraints files generated by Coregen
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echo 'Copying files from constraints directory to results directory'
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cp ../example_design/pll_pal_exdes.ucf results/
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cd results
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echo 'Running ngdbuild'
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ngdbuild -uc pll_pal_exdes.ucf pll_pal_exdes
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echo 'Running map'
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map -timing pll_pal_exdes -o mapped.ncd
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echo 'Running par'
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par -w mapped.ncd routed mapped.pcf
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echo 'Running trce'
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trce -e 10 routed -o routed mapped.pcf
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echo 'Running design through bitgen'
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bitgen -w routed
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echo 'Running netgen to create gate level model for the clocking wizard example design'
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netgen -ofmt vhdl -sim -tm pll_pal_exdes -w routed.ncd routed.vhd
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cd ..
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