repo2/mist_5200/tb_data/data_io_tb.vhd
| 177 | markw | library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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library std_developerskit ; -- used for to_string
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-- use std_developerskit.std_iopak.all;
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entity data_io_tb is
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end;
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architecture rtl of data_io_tb is
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constant CLK_A_PERIOD : time := 1 us / (1.79*32);
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signal CLK_A : std_logic;
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signal reset_n : std_logic;
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signal spi_clk : std_logic;
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signal spi_ss_io : std_logic_vector(1 downto 0);
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signal spi_miso : std_logic;
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signal spi_mosi : std_logic;
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signal request : std_logic;
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signal write : std_logic;
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signal ready : std_logic;
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signal sector : std_logic_vector(23 downto 0);
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signal addr : std_logic_vector(8 downto 0);
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signal data_out : std_logic_vector(7 downto 0);
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signal data_in : std_logic_vector(7 downto 0);
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signal wr_en : std_logic;
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signal spi_enable : std_logic;
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signal spi_tx_data : std_logic_vector(7 downto 0);
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signal spi_rx_data : std_logic_vector(7 downto 0);
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signal spi_busy : std_logic;
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signal spi_addr : integer;
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begin
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p_clk_gen_a : process
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begin
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clk_a <= '1';
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wait for CLK_A_PERIOD/2;
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clk_a <= '0';
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wait for CLK_A_PERIOD - (CLK_A_PERIOD/2 );
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end process;
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reset_n <= '0', '1' after 1000ns;
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spi_master1 : entity work.spi_master
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generic map(slaves=>2,d_width=>8)
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port map (clock=>clk_a,reset_n=>reset_n,enable=>spi_enable,cpol=>'0',cpha=>'0',cont=>'0',clk_div=>4,addr=>spi_addr,
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tx_data=>spi_tx_data, miso=>spi_miso,sclk=>spi_clk,ss_n=>spi_ss_io,mosi=>spi_mosi,
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rx_data=>spi_rx_data,busy=>spi_busy);
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spi_fake : process
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variable type_conv : std_logic_vector(8 downto 0);
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begin
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spi_enable <= '0';
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spi_addr <= 0;
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wait for 1500us;
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spi_tx_data <= x"50";
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spi_enable <= '1';
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wait for CLK_A_PERIOD*2;
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spi_tx_data <= x"FF";
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spi_enable <= '0';
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wait until spi_busy='0';
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for i in 0 to 3 loop
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spi_tx_data <= x"ff";
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spi_enable <= '1';
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wait for CLK_A_PERIOD*2;
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spi_tx_data <= x"FF";
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spi_enable <= '0';
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wait until spi_busy='0';
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end loop;
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spi_addr <= 1;
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spi_tx_data <= x"ff";
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spi_enable <= '1';
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wait for CLK_A_PERIOD*2;
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spi_tx_data <= x"FF";
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spi_enable <= '0';
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wait until spi_busy='0';
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spi_addr <= 0;
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wait for 20us;
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spi_tx_data <= x"51";
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spi_enable <= '1';
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wait for CLK_A_PERIOD*2;
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spi_tx_data <= x"FF";
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spi_enable <= '0';
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wait until spi_busy='0';
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for i in 0 to 511 loop
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type_conv := std_logic_vector(to_unsigned(i,9));
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spi_tx_data <= type_conv(7 downto 0);
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spi_enable <= '1';
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wait for CLK_A_PERIOD*4;
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spi_tx_data <= x"FF";
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spi_enable <= '0';
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wait until spi_busy='0';
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end loop;
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spi_tx_data <= x"ff";
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spi_enable <= '1';
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wait for CLK_A_PERIOD*2;
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spi_tx_data <= x"FF";
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spi_enable <= '0';
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wait until spi_busy='0';
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-- NEXT
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spi_addr <= 1;
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spi_tx_data <= x"ff";
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spi_enable <= '1';
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wait for CLK_A_PERIOD*2;
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spi_tx_data <= x"FF";
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spi_enable <= '0';
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wait until spi_busy='0';
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spi_addr <= 0;
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wait for 20us;
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spi_tx_data <= x"50";
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spi_enable <= '1';
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wait for CLK_A_PERIOD*2;
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spi_tx_data <= x"FF";
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spi_enable <= '0';
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wait until spi_busy='0';
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for i in 0 to 3 loop
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spi_tx_data <= x"ff";
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spi_enable <= '1';
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wait for CLK_A_PERIOD*2;
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spi_tx_data <= x"FF";
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spi_enable <= '0';
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wait until spi_busy='0';
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end loop;
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spi_addr <= 1;
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spi_tx_data <= x"ff";
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spi_enable <= '1';
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wait for CLK_A_PERIOD*2;
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spi_tx_data <= x"FF";
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spi_enable <= '0';
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wait until spi_busy='0';
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spi_addr <= 0;
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wait for 20us;
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spi_tx_data <= x"51";
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spi_enable <= '1';
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wait for CLK_A_PERIOD*2;
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spi_tx_data <= x"FF";
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spi_enable <= '0';
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wait until spi_busy='0';
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for i in 0 to 511 loop
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type_conv := std_logic_vector(to_unsigned(511-i,9));
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spi_tx_data <= type_conv(7 downto 0);
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spi_enable <= '1';
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wait for CLK_A_PERIOD*4;
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spi_tx_data <= x"FF";
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spi_enable <= '0';
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wait until spi_busy='0';
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end loop;
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spi_tx_data <= x"ff";
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spi_enable <= '1';
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wait for CLK_A_PERIOD*2;
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spi_tx_data <= x"FF";
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spi_enable <= '0';
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wait until spi_busy='0';
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-- NEXT - WRITE...
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spi_addr <= 1;
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spi_tx_data <= x"ff";
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spi_enable <= '1';
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wait for CLK_A_PERIOD*2;
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spi_tx_data <= x"FF";
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spi_enable <= '0';
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wait until spi_busy='0';
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spi_addr <= 0;
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wait for 20us;
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spi_tx_data <= x"50";
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spi_enable <= '1';
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wait for CLK_A_PERIOD*2;
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spi_tx_data <= x"FF";
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spi_enable <= '0';
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wait until spi_busy='0';
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for i in 0 to 3 loop
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spi_tx_data <= x"ff";
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spi_enable <= '1';
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wait for CLK_A_PERIOD*2;
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spi_tx_data <= x"FF";
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spi_enable <= '0';
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wait until spi_busy='0';
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end loop;
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spi_addr <= 1;
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spi_tx_data <= x"ff";
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spi_enable <= '1';
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wait for CLK_A_PERIOD*2;
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spi_tx_data <= x"FF";
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spi_enable <= '0';
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wait until spi_busy='0';
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spi_addr <= 0;
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wait for 20us;
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spi_tx_data <= x"52";
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spi_enable <= '1';
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wait for CLK_A_PERIOD*2;
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spi_tx_data <= x"FF";
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spi_enable <= '0';
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wait until spi_busy='0';
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for i in 0 to 511 loop
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spi_tx_data <= x"FF";
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spi_enable <= '1';
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wait for CLK_A_PERIOD*4;
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spi_tx_data <= x"FF";
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spi_enable <= '0';
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wait until spi_busy='0';
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end loop;
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spi_tx_data <= x"ff";
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spi_enable <= '1';
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wait for CLK_A_PERIOD*2;
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spi_tx_data <= x"FF";
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spi_enable <= '0';
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wait until spi_busy='0';
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wait for 100ms;
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end process;
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spi_request : process
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begin
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sector <= (others=>'0');
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request <= '0';
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write <= '0';
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wait for 1500us;
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sector <= x"123456";
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request <= '1';
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wait until ready = '1';
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request <= '0';
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wait for CLK_A_PERIOD*20;
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wait until ready = '0';
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sector <= x"654321";
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request <= '1';
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wait until ready = '1';
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request <= '0';
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wait for CLK_A_PERIOD*20;
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wait until ready = '0';
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sector <= x"111111";
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write <= '1';
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wait until ready = '1';
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write <= '0';
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wait for CLK_A_PERIOD*20;
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wait until ready = '0';
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wait for 100ms;
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end process;
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ram : entity work.generic_ram_infer
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generic map
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(
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ADDRESS_WIDTH => 9,
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SPACE => 512,
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DATA_WIDTH => 8
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)
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PORT map
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(
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clock => spi_clk,
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data => data_out,
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address => addr,
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we => wr_en,
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q => data_in
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);
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data_io : entity work.data_io
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PORT MAP
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(
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CLK => spi_clk,
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RESET_n =>reset_n,
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-- SPI connection - up to upstream to make miso 'Z' on ss_io going high
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SPI_CLK => spi_clk,
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SPI_SS_IO => spi_ss_io(0),
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SPI_MISO => spi_miso,
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SPI_MOSI => spi_mosi,
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-- Sector access request
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read_request => request,
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write_request => write,
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sector => sector,
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ready => ready,
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-- DMA to RAM
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ADDR => addr,
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DATA_OUT => data_out,
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DATA_IN => data_in,
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WR_EN => wr_en
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);
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end rtl;
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