repo2/mcc216_5200/atari5200core.sdc
| 288 | markw | create_clock -period 5MHz [get_ports FPGA_CLK]
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derive_pll_clocks
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| 902 | markw | derive_clock_uncertainty
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set_clock_groups -asynchronous \
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-group { FPGA_CLK } \
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-group { \
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\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]
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\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]
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\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]
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\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]
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} \
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-group { \
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usb_pll|altpll_component|auto_generated|pll1|clk[0]
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}
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