repo2/firmware_eclairexl/linux/emulate_usb.c
| 754 | markw | #include "memory.h"
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#include "integer.h"
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#include "log.h"
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#include <sys/time.h>
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char * usbregname[] =
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{
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"HOST_TX_CONTROL_REG", //0
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"HOST_TX_TRANS_TYPE_REG", //1
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"HOST_TX_LINE_CONTROL_REG", //2
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"HOST_TX_TX_SOF_ENABLE_REG", //3
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"HOST_TX_ADDR_REG", //4
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"HOST_TX_ENDP_REG", //5
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"HOST_FRAME_NUM_MSP_REG", //6
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"HOST_FRAME_NUM_LSP_REG", //7
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"HOST_INTERRUPT_STATUS_REG", //8
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"HOST_INTERRUPT_MASK_REG", //9
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"HOST_RX_STATUS_REG", //a
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"HOST_RX_PID_REG", //b
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"HOST_RX_ADDR_REG", //c
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"HOST_RX_ENDP_REG", //d
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"HOST_RX_CONNEXT_STATE_REG", //e
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"HOST_SOF_TIMER_MSB_REG", //f
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"","","","","","","","",
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"","","","","","","","",
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"HOST_RX_FIFO_DATA", //0x20
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"", //0x21
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"HOST_RX_FIFO_DATA_COUNT_MSB", //0x22
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"HOST_RX_FIFO_DATA_COUNT_LSB", //0x23
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"HOST_RX_FIFO_CONTROL_REG", //0x24
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"","","",
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"","","","","","","","",
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"HOST_TX_FIFO_DATA", //0x30
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"", //0x31
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"", //0x32
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"", //0x33
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"HOST_TX_FIFO_CONTROL_REG", //0x34
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"","","",
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"","","","","","","",""
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"","","","","","","","", //0x40
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"","","","","","","","",
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"","","","","","","","", //0x50
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"","","","","","","","",
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"","","","","","","","", //0x60
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"","","","","","","","",
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"","","","","","","","", //0x70
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"","","","","","","","",
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"","","","","","","","", //0x80
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"","","","","","","","",
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"","","","","","","","", //0x90
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"","","","","","","","",
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"","","","","","","","", //0xa0
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"","","","","","","","",
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"","","","","","","","", //0xb0
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"","","","","","","","",
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"","","","","","","","", //0xc0
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"","","","","","","","",
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"","","","","","","","", //0xd0
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"","","","","","","","",
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"HOST_SLAVE_CONTROL_REG", // 0xe0
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"HOST_SLAVE_VERSION_REG",
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"","","","","","",
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"","","","","","","","",
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"","","","","","","","", //0xf0
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"","","","","","","",""
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};
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#define HOST_TX_CONTROL_REG 0x0
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#define HOST_TX_TRANS_TYPE_REG 0x1
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#define HOST_TX_LINE_CONTROL_REG 0x2
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#define HOST_TX_SOF_ENABLE_REG 0x3
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#define HOST_INTERRUPT_STATUS_REG 0x8
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#define HOST_RX_CONNECT_STATE_REG 0xe
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#define HOST_RX_STATUS_REG 0xa
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#define HOST_RX_FIFO_DATA 0x20
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#define HOST_RX_FIFO_CONTROL_REG 0x24
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#define HOST_RX_FIFO_COUNT_LSB 0x23
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#define HOST_TX_FIFO_DATA 0x30
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#define HOST_TX_FIFO_CONTROL_REG 0x34
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# define OHS900_SETUP 0x00
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# define OHS900_IN 0x01
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# define OHS900_OUT_DATA0 0x02
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# define OHS900_OUT_DATA1 0x03
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# define OHS900_INTMASK_TRANS_DONE 0x01
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# define OHS900_INTMASK_SOFINTR 0x08
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# define OHS900_INTMASK_INSRMV 0x04
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# define OHS900_INTMASK_RESUME_DET 0x02
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uint8_t txfifo[64];
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uint8_t txfifolen = 0;
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uint8_t rxfifo[64];
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uint8_t rxfifopos = 0;
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uint8_t regs[256];
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double transmit_complete_time = 0.0;
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int in_pending = 0;
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int out_pending = 0;
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int setup_pending = 0;
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int first = true;
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char data[]
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=
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{
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0,0x80,
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8,0x80,0x12,0x01,0x00,0x01,0x00,0x00,0x00,0x08,
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8,0x80,0x12,0x01,0x00,0x01,0x00,0x00,0x00,0x08,
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8,0,0x79,0x00,0x06,0x00,0x07,0x01,0x01,0x02,
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2,0x80,0x00,0x01,
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8,0x80,0x09,0x02,0x29,0x00,0x01,0x01,0x00,0x80,
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1,0,0xfa,
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8,0x80,0x09,0x02,0x29,0x00,0x01,0x01,0x00,0x80,
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8,0x00,0xfa,0x09,0x04,0x00,0x00,0x02,0x03,0x00,
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8,0x80,0x00,0x00,0x09,0x21,0x10,0x01,0x21,0x01,
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8,0x00,0x22,0x6b,0x00,0x07,0x05,0x81,0x03,0x08,
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8,0x80,0x00,0x0a,0x07,0x05,0x01,0x03,0x08,0x00,
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1,0,0x0a
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};
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int datapos = 0;
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char outdata[]
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=
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{
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0x40,0x40,0x40,0x40,
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0x40,0x40,0x40,0x40,
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0x40,0x40,0x40,0x40,
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0x40,0x40,0x40,0x40,
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0x40,0x40,0x40,0x40
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};
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int outdatapos = 0;
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void usbhostslave_init()
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{
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first = false;
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int i;
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for (i=0; i!=256;++i) regs[i] = 0 ;
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}
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double now()
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{
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struct timeval tv;
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gettimeofday(&tv,0);
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double res = tv.tv_sec;
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res += (double)tv.tv_usec/1e6;;
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return res;
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}
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void usbhostslave_update()
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{
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if (now()>transmit_complete_time)
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{
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int i;
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if (in_pending)
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{
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in_pending = 0;
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int len = data[datapos++];
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LOG("IN DONE - received %d bytes: ", len);
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u08 stator = data[datapos++];
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for (i=0;i!=len; ++i)
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{
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uint8_t val = data[datapos++];
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LOG("%02x",val);
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rxfifo[regs[HOST_RX_FIFO_COUNT_LSB]++] = val;
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}
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LOG("\n");
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regs[HOST_INTERRUPT_STATUS_REG] |= OHS900_INTMASK_TRANS_DONE;
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regs[HOST_RX_STATUS_REG] = stator;
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}
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if (out_pending)
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{
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out_pending = 0;
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regs[HOST_INTERRUPT_STATUS_REG] |= OHS900_INTMASK_TRANS_DONE;
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regs[HOST_RX_STATUS_REG] = outdata[outdatapos++];
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LOG("OUT DONE - sent ");
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for (i=0;i!=txfifolen; ++i)
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{
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LOG("%02x",txfifo[i]);
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}
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LOG("\n");
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txfifolen = 0;
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}
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if (setup_pending)
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{
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setup_pending = 0;
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regs[HOST_INTERRUPT_STATUS_REG] |= OHS900_INTMASK_TRANS_DONE;
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regs[HOST_RX_STATUS_REG] = 0x40;
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LOG("SETUP DONE - sent ");
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for (i=0;i!=txfifolen; ++i)
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{
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LOG("%02x",txfifo[i]);
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}
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LOG("\n");
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txfifolen = 0;
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}
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}
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}
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void usbhostslave_write(int address, uint8_t val)
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{
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usbhostslave_update();
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int realAddress = address/4;
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if (first) usbhostslave_init();
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switch (realAddress)
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{
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case HOST_TX_CONTROL_REG:
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if (val&0x1) // transmit request!
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{
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switch (regs[HOST_TX_TRANS_TYPE_REG] & OHS900_OUT_DATA1)
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{
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case OHS900_SETUP:
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LOG("SETUP\n");
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setup_pending = true;
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break;
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case OHS900_IN:
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LOG("IN\n");
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in_pending = true;
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break;
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case OHS900_OUT_DATA0:
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LOG("OUT_DATA0\n");
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out_pending = true;
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break;
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case OHS900_OUT_DATA1:
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LOG("OUT_DATA1\n");
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out_pending = true;
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break;
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}
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transmit_complete_time = now(); //+10e-6;;
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}
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else
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{
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LOG("NON transmit write to control??");
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}
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break;
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case HOST_RX_FIFO_CONTROL_REG:
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if (val == 1)
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{
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txfifolen = 0;
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}
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break;
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case HOST_TX_FIFO_DATA:
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if (txfifolen<sizeof(txfifo))
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{
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txfifo[txfifolen++] = val;
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}
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break;
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case HOST_TX_FIFO_CONTROL_REG:
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if (val == 1)
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{
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txfifolen = 0;
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}
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break;
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default:
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//LOG("Write %02x to %s\n", val, usbregname[realAddress]);
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regs[realAddress] = val;
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break;
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}
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}
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uint8_t usbhostslave_read(int address)
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{
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usbhostslave_update();
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int realAddress = address/4;
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if (first) usbhostslave_init();
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switch (realAddress)
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{
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case HOST_RX_CONNECT_STATE_REG:
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{
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static int count = 0;
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++count;
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if (count == 4)
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{
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LOG("Reading from %s - CONNECTED (suppressing...)\n", usbregname[realAddress]);
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}
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if (count > 3)
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{
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return 2;
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}
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//LOG("Reading from %s\n", usbregname[realAddress]);
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return 0;
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}
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break;
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case HOST_RX_FIFO_DATA:
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{
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uint8_t val = rxfifo[rxfifopos++];
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if (rxfifopos == regs[HOST_RX_FIFO_COUNT_LSB])
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{
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rxfifopos = 0;
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regs[HOST_RX_FIFO_COUNT_LSB] = 0;
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}
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return val;
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}
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break;
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default:
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//LOG("Reading from %s\n", usbregname[realAddress]);
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return regs[realAddress];
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}
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}
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