/eclaireXL_ITX/hdmi/hdmi_line_buffer.cmp - Annotate - EclaireXL - 64kib

repo2/eclaireXL_ITX/hdmi/hdmi_line_buffer.cmp

-            markw
+--Copyright (C) 2018  Intel Corporation. All rights reserved.
-            markw
+--Your use of Intel Corporation's design tools, logic functions
 --and other software and tools, and its AMPP partner logic
 --functions, and any output files from any of the foregoing
 --(including device programming or simulation files), and any
 --associated documentation or information are expressly subject
 --to the terms and conditions of the Intel Program License
 --Subscription Agreement, the Intel Quartus Prime License Agreement,
-            markw
+--the Intel FPGA IP License Agreement, or other applicable license
 --agreement, including, without limitation, that your use is for
 --the sole purpose of programming logic devices manufactured by
 --Intel and sold by Intel or its authorized distributors.  Please
 --refer to the applicable agreement for further details.
             markw
 component hdmi_line_buffer
 	PORT
+	(
 		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-            markw
+		rdaddress		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
-            markw
+		rdclock		: IN STD_LOGIC ;
-            markw
+		wraddress		: IN STD_LOGIC_VECTOR (13 DOWNTO 0);
-            markw
+		wrclock		: IN STD_LOGIC  := '1';
 		wren		: IN STD_LOGIC  := '0';
-            markw
+		q		: OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
-            markw
+	);
 end component;