repo2/eclaireXL_ITX/gpio_debug.vhd
| 599 | markw | -- (c) 2017 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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LIBRARY work;
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ENTITY gpio_debug IS
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PORT
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(
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CLK : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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PBI_DEBUG : IN STD_LOGIC_VECTOR(31 downto 0);
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PBI_DEBUG_READY : IN STD_LOGIC;
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DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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CLK_OUT : OUT STD_LOGIC
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);
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END gpio_debug;
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ARCHITECTURE vhdl OF gpio_debug IS
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signal cycle_reg : std_logic_vector(4 downto 0);
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signal cycle_next : std_logic_vector(4 downto 0);
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signal pbi_debug_reg : std_logic_vector(31 downto 0);
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signal pbi_debug_next : std_logic_vector(31 downto 0);
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| 600 | markw | signal data_out_reg : std_logic_vector(7 downto 0);
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signal data_out_next : std_logic_vector(7 downto 0);
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| 599 | markw | ||
signal clk_out_reg : std_logic;
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signal clk_out_next : std_logic;
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BEGIN
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process(clk,reset_n)
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begin
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if (reset_n='0') then
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pbi_debug_reg <= (others=>'0');
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cycle_reg <= (others=>'0');
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data_out_reg <= (others=>'0');
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clk_out_reg <= '0';
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| 600 | markw | elsif (clk'event and clk='1') then
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| 599 | markw | pbi_debug_reg <= pbi_debug_next;
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cycle_reg <= cycle_next;
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data_out_reg <= data_out_next;
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clk_out_reg <= clk_out_next;
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end if;
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end process;
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process(cycle_reg,pbi_debug_ready,pbi_debug,pbi_debug_reg,data_out_reg,clk_out_reg)
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begin
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| 600 | markw | pbi_debug_next <= pbi_debug_reg;
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| 599 | markw | cycle_next <= std_logic_vector(unsigned(cycle_reg)+1);
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data_out_next <= data_out_reg;
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clk_out_next <= clk_out_reg;
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| 600 | markw | if (pbi_debug_ready='1') then
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| 599 | markw | cycle_next <= (others=>'0');
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pbi_debug_next <= pbi_debug;
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end if;
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case cycle_reg is
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| 600 | markw | when "0"&x"0" =>
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| 599 | markw | data_out_next <= pbi_debug_reg(7 downto 0);
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| 600 | markw | when "0"&x"4" =>
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clk_out_next <= not(clk_out_reg);
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when "0"&x"8" =>
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| 599 | markw | data_out_next <= pbi_debug_reg(15 downto 8);
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| 600 | markw | when "0"&x"c" =>
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clk_out_next <= not(clk_out_reg);
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when "1"&x"0" =>
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| 599 | markw | data_out_next <= pbi_debug_reg(23 downto 16);
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| 600 | markw | when "1"&x"4" =>
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clk_out_next <= not(clk_out_reg);
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when "1"&x"8" =>
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| 599 | markw | data_out_next <= pbi_debug_reg(31 downto 24);
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| 600 | markw | when "1"&x"c" =>
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clk_out_next <= not(clk_out_reg);
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when others =>
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| 599 | markw | end case;
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end process;
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data_out <= data_out_reg;
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clk_out <= clk_out_reg;
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END vhdl;
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