repo2/eclaireXL_ITX/ddioclkctrl/ddioclkctrl_inst.vhd
| 479 | markw | component ddioclkctrl is
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port (
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inclk3x : in std_logic := 'X'; -- inclk3x
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inclk2x : in std_logic := 'X'; -- inclk2x
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inclk1x : in std_logic := 'X'; -- inclk1x
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inclk0x : in std_logic := 'X'; -- inclk0x
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clkselect : in std_logic_vector(1 downto 0) := (others => 'X'); -- clkselect
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ena : in std_logic := 'X'; -- ena
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outclk : out std_logic -- outclk
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);
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end component ddioclkctrl;
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u0 : component ddioclkctrl
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port map (
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inclk3x => CONNECTED_TO_inclk3x, -- altclkctrl_input.inclk3x
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inclk2x => CONNECTED_TO_inclk2x, -- .inclk2x
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inclk1x => CONNECTED_TO_inclk1x, -- .inclk1x
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inclk0x => CONNECTED_TO_inclk0x, -- .inclk0x
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clkselect => CONNECTED_TO_clkselect, -- .clkselect
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ena => CONNECTED_TO_ena, -- .ena
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outclk => CONNECTED_TO_outclk -- altclkctrl_output.outclk
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);
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