repo2/eclaireXL_ITX/clkctrl2/clkctrl2_generation.rpt
| 974 | markw | Info: Starting: Create block symbol file (.bsf)
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Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/eclaireXL_ITX/build_A4EBArom/clkctrl2.qsys --block-symbol-file --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/eclaireXL_ITX/build_A4EBArom/clkctrl2 --family="Cyclone V" --part=5CEBA4F23C8
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Progress: Loading build_A4EBArom/clkctrl2.qsys
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Progress: Reading input file
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Progress: Adding altclkctrl_0 [altclkctrl 18.0]
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Progress: Parameterizing module altclkctrl_0
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Progress: Building connections
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Progress: Parameterizing connections
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Progress: Validating
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Progress: Done reading input file
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: clkctrl2.altclkctrl_0: Targeting device family: Cyclone V.
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: clkctrl2.altclkctrl_0: Selecting AUTO allows the compiler to pick the best clock buffer to use, while other values restrict usage to only the given clock buffer.
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: clkctrl2.altclkctrl_0: The register mode of port 'ena' is unavailable while 'ena' port not added.
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Info: qsys-generate succeeded.
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Info: Finished: Create block symbol file (.bsf)
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Info:
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Info: Starting: Create HDL design files for synthesis
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Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/eclaireXL_ITX/build_A4EBArom/clkctrl2.qsys --synthesis=VHDL --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/eclaireXL_ITX/build_A4EBArom/clkctrl2/synthesis --family="Cyclone V" --part=5CEBA4F23C8
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Progress: Loading build_A4EBArom/clkctrl2.qsys
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Progress: Reading input file
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Progress: Adding altclkctrl_0 [altclkctrl 18.0]
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Progress: Parameterizing module altclkctrl_0
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Progress: Building connections
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Progress: Parameterizing connections
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Progress: Validating
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Progress: Done reading input file
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: clkctrl2.altclkctrl_0: Targeting device family: Cyclone V.
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: clkctrl2.altclkctrl_0: Selecting AUTO allows the compiler to pick the best clock buffer to use, while other values restrict usage to only the given clock buffer.
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: clkctrl2.altclkctrl_0: The register mode of port 'ena' is unavailable while 'ena' port not added.
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Info: clkctrl2: Generating clkctrl2 "clkctrl2" for QUARTUS_SYNTH
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Info: altclkctrl_0: Generating top-level entity clkctrl2_altclkctrl_0.
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Info: altclkctrl_0: "clkctrl2" instantiated altclkctrl "altclkctrl_0"
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Info: clkctrl2: Done "clkctrl2" with 2 modules, 2 files
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Info: qsys-generate succeeded.
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Info: Finished: Create HDL design files for synthesis
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