repo2/eclaireXL_ITX/atari800core_eclaireXLproto.vhd
| 479 | markw | ---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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LIBRARY work;
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ENTITY atari800core_eclaireXLproto IS
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GENERIC
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(
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hdmiOnGPIO : integer := 0;
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internal_rom : integer := 1; -- if 0 expects it in sdram,is 1:16k os+basic, is 2:... TODO
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internal_ram : integer := 16384 -- at start of memory map
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);
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PORT
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(
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CLOCK_5 : IN STD_LOGIC;
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PS2CLK : IN STD_LOGIC;
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PS2DAT : IN STD_LOGIC;
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GPIOA : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
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GPIOB : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
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GPIOC: INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
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DRAM_BA_0 : OUT STD_LOGIC;
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DRAM_BA_1 : OUT STD_LOGIC;
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DRAM_CS_N : OUT STD_LOGIC;
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DRAM_RAS_N : OUT STD_LOGIC;
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DRAM_CAS_N : OUT STD_LOGIC;
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DRAM_WE_N : OUT STD_LOGIC;
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DRAM_LDQM : OUT STD_LOGIC;
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DRAM_UDQM : OUT STD_LOGIC;
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DRAM_CLK : OUT STD_LOGIC;
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DRAM_CKE : OUT STD_LOGIC;
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DRAM_ADDR : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
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DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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SD_WRITEPROTECT : IN STD_LOGIC;
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SD_DETECT : IN STD_LOGIC;
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SD_DAT1 : OUT STD_LOGIC;
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SD_DAT0 : IN STD_LOGIC;
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SD_CLK : OUT STD_LOGIC;
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SD_CMD : OUT STD_LOGIC;
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SD_DAT3 : OUT STD_LOGIC;
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SD_DAT2 : OUT STD_LOGIC;
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VGA_VS : OUT STD_LOGIC;
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VGA_HS : OUT STD_LOGIC;
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VGA_B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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VGA_G : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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VGA_R : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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VGA_BLANK_N : OUT STD_LOGIC;
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VGA_CLK : OUT STD_LOGIC;
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AUDIO_LEFT : OUT STD_LOGIC;
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AUDIO_RIGHT : OUT STD_LOGIC;
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USB2DM: INOUT STD_LOGIC;
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USB2DP: INOUT STD_LOGIC;
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USB1DM: INOUT STD_LOGIC;
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USB1DP: INOUT STD_LOGIC;
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ADC_SDA: INOUT STD_LOGIC;
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ADC_SCL: INOUT STD_LOGIC
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);
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END atari800core_eclaireXLproto;
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ARCHITECTURE vhdl OF atari800core_eclaireXLproto IS
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component pll_gclk
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port (
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refclk : in std_logic := '0'; -- refclk.clk
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rst : in std_logic := '0'; -- reset.reset
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outclk_0 : out std_logic -- outclk0.clk
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);
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end component;
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signal ADAPTCLOCK_50 : std_logic;
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signal POTRESET : std_logic;
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signal TRIG : std_logic_vector(1 downto 0);
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signal POTIN : std_logic_vector(3 downto 0);
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signal VGA_Rint : std_logic_vector(7 downto 0);
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signal VGA_Bint : std_logic_vector(7 downto 0);
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BEGIN
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newboard : work.atari800core_eclaireXL
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GENERIC MAP
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(
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internal_rom => internal_rom,
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internal_ram => internal_ram
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)
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PORT MAP
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(
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CLOCK_50 => ADAPTCLOCK_50,
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GPIOA => open,
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EXP => open,
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PBI_A(15) => GPIOB(31),
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PBI_A(14) => GPIOB(30),
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PBI_A(13) => GPIOB(29),
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PBI_A(12) => GPIOB(11),
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PBI_A(11) => GPIOB(5),
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PBI_A(10) => GPIOB(4),
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PBI_A(9) => GPIOB(13),
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PBI_A(8) => GPIOB(15),
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PBI_A(7) => GPIOB(17),
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PBI_A(6) => GPIOB(19),
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PBI_A(5) => GPIOB(21),
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PBI_A(4) => GPIOB(23),
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PBI_A(3) => GPIOB(25),
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PBI_A(2) => GPIOB(24),
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PBI_A(1) => GPIOB(22),
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PBI_A(0) => GPIOB(20),
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PBI_D(7) => GPIOB(7),
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PBI_D(6) => GPIOB(8),
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PBI_D(5) => GPIOB(16),
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PBI_D(4) => GPIOB(18),
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PBI_D(3) => GPIOB(9),
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PBI_D(2) => GPIOB(14),
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PBI_D(1) => GPIOB(12),
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PBI_D(0) => GPIOB(10),
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PBI_CLK => GPIOB(1),
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PBI_RW_N => GPIOB(3),
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PBI_EXTSEL_N => GPIOB(28),
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PBI_MPD_N => GPIOB(32),
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PBI_REF_N => GPIOB(33),
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PBI_IRQ_N => GPIOB(34),
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PBI_RST_N => GPIOB(35),
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CART_S4_N => GPIOB(27),
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CART_S5_N => GPIOB(6),
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CART_RD4 => GPIOB(26),
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CART_RD5 => GPIOB(2),
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CART_CCTL_N => GPIOB(0),
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SIO_CLOCKIN => GPIOA(7),
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SIO_CLOCKOUT => GPIOA(6),
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SIO_IN => GPIOA(5),
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SIO_IRQ => GPIOA(0),
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SIO_OUT => GPIOA(4),
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SIO_COMMAND => GPIOA(1),
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SIO_PROCEED => GPIOA(2),
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SIO_MOTOR_RAW => GPIOA(3),
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SER_CMD => open,
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SER_TX => open,
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SER_RX => '1',
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PORTA(7) => GPIOA(8),
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PORTA(6) => GPIOA(9),
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PORTA(5) => GPIOA(10),
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PORTA(4) => GPIOA(11),
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PORTA(3) => GPIOA(17),
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PORTA(2) => GPIOA(18),
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PORTA(1) => GPIOA(19),
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PORTA(0) => GPIOA(20),
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TRIG => TRIG,
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POTIN => POTIN,
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POTRESET => POTRESET,
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DRAM_BA_0 => DRAM_BA_0,
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DRAM_BA_1 => DRAM_BA_1,
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DRAM_CS_N => DRAM_CS_N,
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DRAM_RAS_N => DRAM_RAS_N,
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DRAM_CAS_N => DRAM_CAS_N,
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DRAM_WE_N => DRAM_WE_N,
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DRAM_LDQM => DRAM_LDQM,
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DRAM_UDQM => DRAM_UDQM,
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DRAM_CLK => DRAM_CLK,
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DRAM_CKE => DRAM_CKE,
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DRAM_ADDR => DRAM_ADDR,
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DRAM_DQ => DRAM_DQ,
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SD_WRITEPROTECT => SD_WRITEPROTECT,
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SD_DETECT => SD_DETECT,
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SD_DAT1 => SD_DAT1,
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SD_DAT0 => SD_DAT0,
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SD_CLK => SD_CLK,
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SD_CMD => SD_CMD,
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SD_DAT3 => SD_DAT3,
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SD_DAT2 => SD_DAT2,
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VGA_VS => VGA_VS,
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VGA_HS => VGA_HS,
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VGA_B => VGA_Bint,
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VGA_G => VGA_G,
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VGA_R => VGA_Rint,
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VGA_BLANK_N => VGA_BLANK_N,
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VGA_CLK => VGA_CLK,
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AUDIO_LEFT => AUDIO_LEFT,
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AUDIO_RIGHT => AUDIO_RIGHT,
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USB2DM => USB2DM,
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USB2DP => USB2DP,
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USB1DM => USB1DM,
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USB1DP => USB1DP,
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ADC_SDA => open,
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ADC_SCL => open
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);
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TRIG <= GPIOA(12)&GPIOA(21);
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GPIOA(12) <= 'Z';
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GPIOA(21) <= 'Z';
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POTIN <= GPIOA(13)&GPIOA(14)&GPIOA(15)&GPIOA(16);
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GPIOA(16 downto 13) <= "0000" when POTRESET='1' else "ZZZZ";
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gen_no_hdmi : if hdmiOnGPIO=0 generate
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VGA_R <= VGA_Rint;
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VGA_B <= VGA_Bint;
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end generate gen_no_hdmi;
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gen_hdmi : if hdmiOnGPIO=1 generate
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VGA_R(7) <= VGA_Rint(7);
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VGA_R(6) <= VGA_Rint(6);
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VGA_R(5) <= VGA_Rint(5);
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--VGA_R(4) <= VGA_Rint(4);
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--VGA_R(3) <= VGA_Rint(3);
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VGA_R(2) <= VGA_Rint(2);
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--VGA_R(1) <= VGA_Rint(1);
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--VGA_R(0) <= VGA_Rint(0);
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VGA_B(7) <= VGA_Bint(7);
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--VGA_B(6) <= VGA_Bint(6);
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--VGA_B(5) <= VGA_Bint(5);
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--VGA_B(4) <= VGA_Bint(4);
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VGA_B(3) <= VGA_Bint(3);
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VGA_B(2) <= VGA_Bint(2);
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--VGA_B(1) <= VGA_Bint(1);
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VGA_B(0) <= VGA_Bint(0);
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GPIOC(1) <= VGA_Rint(0); -- D2P
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GPIOC(2) <= VGA_Rint(1); -- D2N
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GPIOC(3) <= VGA_Rint(4); -- D1P
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GPIOC(4) <= VGA_Rint(3); -- D1N
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GPIOC(12) <= VGA_Bint(1); -- D0N
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GPIOC(13) <= VGA_Bint(4); -- D0P
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GPIOC(14) <= VGA_Bint(5); -- C N
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GPIOC(15) <= VGA_Bint(6); -- C P
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end generate gen_hdmi;
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pll_gclk_inst : pll_gclk -- upscale clock from 5 to 50MHz and put on global clock line - so we can use more plls and fractional features!
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PORT MAP(refclk => CLOCK_5,
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outclk_0 => ADAPTCLOCK_50);
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END vhdl;
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