repo2/de1_5200/hexdecoder.vhd
| 176 | markw | ---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY hexdecoder IS
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PORT
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(
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CLK : IN STD_LOGIC;
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NUMBER : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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DIGIT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
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);
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END hexdecoder;
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ARCHITECTURE vhdl OF hexdecoder IS
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signal numinv : STD_LOGIC_VECTOR(3 downto 0);
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signal digit_next : std_logic_vector(6 downto 0);
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signal digit_reg : STD_LOGIC_VECTOR(6 DOWNTO 0);
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BEGIN
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--numinv <= not(NUMBER);
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numinv <= NUMBER;
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process(numinv)
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begin
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case numinv is
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when "0000" =>
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digit_next <= "1111111";
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when "0001" =>
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digit_next <= "1111001";
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when "0010" =>
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digit_next <= "0100100";
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when "0011" =>
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digit_next <= "0110000";
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when "0100" =>
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digit_next <= "0011001";
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when "0101" =>
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digit_next <= "0010010";
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when "0110" =>
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digit_next <= "0000010";
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when "0111" =>
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digit_next <= "1111000";
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when "1000" =>
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digit_next <= "0000000";
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when "1001" =>
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digit_next <= "0011000";
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when "1010" =>
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digit_next <= "0001000";
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when "1011" =>
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digit_next <= "0000011";
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when "1100" =>
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digit_next <= "1000110";
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when "1101" =>
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digit_next <= "0100001";
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when "1110" =>
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digit_next <= "0000110";
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when "1111" =>
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digit_next <= "0001110";
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when others =>
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digit_next <= "1111111";
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end case;
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end process;
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process(clk)
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begin
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if (clk'event and clk='1') then
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digit_reg <= digit_next;
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end if;
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end process;
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digit<=digit_reg;
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END vhdl;
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