repo2/common/components/usbhostslave/trunk/usbDevice/RTL/wishboneArb.v
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//// ////
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//// wishboneArb.v ////
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//// ////
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//// This file is part of the usbHostSlave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// Module Description: ////
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//// Arbitrate between 3 wishbone bus controllers
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//// Uses Round Robin access controller
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////
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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module wishboneArb (
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clk,
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rst,
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addr0_i,
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data0_i,
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stb0_i,
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we0_i,
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req0,
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gnt0,
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addr1_i,
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data1_i,
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stb1_i,
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we1_i,
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req1,
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gnt1,
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addr2_i,
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data2_i,
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stb2_i,
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we2_i,
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req2,
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gnt2,
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addr_o,
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data_o,
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stb_o,
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we_o
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);
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input clk;
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input rst;
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input [7:0] addr0_i;
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input [7:0] data0_i;
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input stb0_i;
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input we0_i;
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input req0;
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output gnt0;
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reg gnt0;
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input [7:0] addr1_i;
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input [7:0] data1_i;
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input stb1_i;
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input we1_i;
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input req1;
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output gnt1;
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reg gnt1;
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input [7:0] addr2_i;
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input [7:0] data2_i;
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input stb2_i;
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input we2_i;
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input req2;
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output gnt2;
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reg gnt2;
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output [7:0] addr_o;
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reg [7:0] addr_o;
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output [7:0] data_o;
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reg [7:0] data_o;
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output stb_o;
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reg stb_o;
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output we_o;
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reg we_o;
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//local wires and regs
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reg [1:0] muxSel;
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reg [2:0] arbSt;
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`define REQ_0 3'b000
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`define REQ_1 3'b001
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`define REQ_2 3'b010
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`define GNT_0 3'b011
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`define GNT_1 3'b100
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`define GNT_2 3'b101
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//arb
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always @(posedge clk) begin
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if (rst == 1'b1) begin
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gnt0 <= 1'b0;
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gnt1 <= 1'b0;
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gnt2 <= 1'b0;
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muxSel <= 2'b00;
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arbSt <= `REQ_0;
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end
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else begin
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case (arbSt)
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`REQ_0: begin
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if (req0 == 1'b1)
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arbSt <= `GNT_0;
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else
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arbSt <= `REQ_1;
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end
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`REQ_1: begin
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if (req1 == 1'b1)
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arbSt <= `GNT_1;
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else
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arbSt <= `REQ_2;
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end
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`REQ_2: begin
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if (req2 == 1'b1)
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arbSt <= `GNT_2;
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else
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arbSt <= `REQ_0;
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end
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`GNT_0: begin
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gnt0 <= 1'b1;
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muxSel <= 2'b00;
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if (req0 == 1'b0) begin
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arbSt <= `REQ_1;
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gnt0 <= 1'b0;
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end
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end
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`GNT_1: begin
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gnt1 <= 1'b1;
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muxSel <= 2'b01;
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if (req1 == 1'b0) begin
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arbSt <= `REQ_2;
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gnt1 <= 1'b0;
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end
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end
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`GNT_2: begin
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gnt2 <= 1'b1;
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muxSel <= 2'b10;
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if (req2 == 1'b0) begin
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arbSt <= `REQ_0;
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gnt2 <= 1'b0;
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end
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end
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endcase
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end
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end
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//mux
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always @(*) begin
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case (muxSel)
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2'b00: begin
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addr_o <= addr0_i;
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data_o <= data0_i;
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stb_o <= stb0_i;
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we_o <= we0_i;
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end
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2'b01: begin
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addr_o <= addr1_i;
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data_o <= data1_i;
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stb_o <= stb1_i;
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we_o <= we1_i;
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end
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2'b10: begin
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addr_o <= addr2_i;
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data_o <= data2_i;
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stb_o <= stb2_i;
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we_o <= we2_i;
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end
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default: begin
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addr_o <= addr0_i;
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data_o <= data0_i;
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stb_o <= stb0_i;
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we_o <= we0_i;
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end
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endcase
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end
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endmodule
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