repo2/common/components/usbhostslave/trunk/usbDevice/RTL/usbDeviceActelTop.v
| 264 | markw | ||
module usbDeviceActelTop (
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//
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// Global signals
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//
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clk,
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rst_n,
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// eval board features
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ledOut,
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//
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// USB
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//
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usbSlaveVP,
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usbSlaveVM,
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usbSlaveOE_n,
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usbDPlusPullup
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);
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//
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// Global signals
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//
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input clk;
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input rst_n;
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output [9:0] ledOut;
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//
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// USB
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//
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inout usbSlaveVP;
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inout usbSlaveVM;
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output usbSlaveOE_n;
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output usbDPlusPullup;
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//local wires and regs
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reg [1:0] rstReg;
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wire rst;
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//generate sync reset
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always @(posedge clk) begin
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rstReg[1:0] <= {rstReg[0], ~rst_n};
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end
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assign rst = rstReg[1];
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usbDevice u_usbDevice (
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.clk(clk),
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.rst(rst),
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.usbSlaveVP_in(usbSlaveVP_in),
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.usbSlaveVM_in(usbSlaveVM_in),
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.usbSlaveVP_out(usbSlaveVP_out),
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.usbSlaveVM_out(usbSlaveVM_out),
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.usbSlaveOE_n(usbSlaveOE_n),
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.usbDPlusPullup(usbDPlusPullup),
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.vBusDetect(1'b1)
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);
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assign {usbSlaveVP_in, usbSlaveVM_in} = {usbSlaveVP, usbSlaveVM};
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assign {usbSlaveVP, usbSlaveVM} = (usbSlaveOE_n == 1'b0) ? {usbSlaveVP_out, usbSlaveVM_out} : 2'bzz;
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// comfort lights
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reg [9:0] ledCntReg;
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reg [21:0] cnt;
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assign ledOut = ledCntReg;
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always @(posedge clk) begin
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if (rst == 1'b1) begin
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ledCntReg <= 10'b00_0000_0000;
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cnt <= {22{1'b0}};
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end
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else begin
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cnt <= cnt + 1'b1;
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if (cnt == {22{1'b0}})
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ledCntReg <= ledCntReg + 1'b1;
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end
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end
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endmodule
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