repo2/common/components/usbhostslave/trunk/usbDevice/RTL/usbDevice.v
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//// ////
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//// usbDevice.v ////
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//// ////
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//// This file is part of the usbHostSlave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// Module Description: ////
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//// Top level module for usbDevice
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//// Instantiates a usbSlave, and controllers for EP0 and EP1
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//// If you wish to implement another type of HID, then you will
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//// need to modify usbROM.v, and EP1Mouse.v
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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module usbDevice (
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clk,
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rst,
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usbSlaveVP_in,
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usbSlaveVM_in,
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usbSlaveVP_out,
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usbSlaveVM_out,
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usbSlaveOE_n,
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USBFullSpeed,
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usbDPlusPullup,
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usbDMinusPullup,
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vBusDetect
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);
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input clk;
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input rst;
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input usbSlaveVP_in;
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input usbSlaveVM_in;
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output usbSlaveVP_out;
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output usbSlaveVM_out;
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output usbSlaveOE_n;
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output USBFullSpeed;
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output usbDPlusPullup;
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output usbDMinusPullup;
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input vBusDetect;
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//local wires and regs
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wire [7:0] wb_addr0;
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wire wb_stb0;
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wire wb_we0;
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wire wbBusReq0;
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wire wbBusGnt0;
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wire [7:0] wb_addr1;
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wire [7:0] wb_data_o1;
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wire wb_stb1;
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wire wb_we1;
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wire wbBusReq1;
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wire wbBusGnt1;
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wire [7:0] wb_addr2;
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wire [7:0] wb_data_o2;
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wire wb_stb2;
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wire wb_we2;
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wire wbBusReq2;
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wire wbBusGnt2;
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wire [7:0] wb_adr;
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wire [7:0] wb_dat_to_usb;
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wire [7:0] wb_dat_from_usb;
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wire wb_we;
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wire wb_stb;
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wire wb_ack;
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reg [1:0] resetReg;
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wire initComplete;
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wire usbRstDet;
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wire [7:0] memAddr;
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wire [7:0] memData;
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wire USBWireCtrlOut;
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wire [1:0] USBWireDataIn;
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wire [1:0] USBWireDataOut;
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//Parameters declaration:
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defparam usbSlaveInst.EP0_FIFO_DEPTH = 64;
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defparam usbSlaveInst.EP0_FIFO_ADDR_WIDTH = 6;
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defparam usbSlaveInst.EP1_FIFO_DEPTH = 64;
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defparam usbSlaveInst.EP1_FIFO_ADDR_WIDTH = 6;
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defparam usbSlaveInst.EP2_FIFO_DEPTH = 64;
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defparam usbSlaveInst.EP2_FIFO_ADDR_WIDTH = 6;
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defparam usbSlaveInst.EP3_FIFO_DEPTH = 64;
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defparam usbSlaveInst.EP3_FIFO_ADDR_WIDTH = 6;
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usbSlave usbSlaveInst (
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.clk_i(clk),
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.rst_i(rst),
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.address_i(wb_adr),
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.data_i(wb_dat_to_usb),
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.data_o(wb_dat_from_usb),
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.we_i(wb_we),
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.strobe_i(wb_stb),
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.ack_o(wb_ack),
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.usbClk(clk),
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.slaveSOFRxedIntOut(),
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.slaveResetEventIntOut(),
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.slaveResumeIntOut(),
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.slaveTransDoneIntOut(),
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.slaveNAKSentIntOut(),
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.slaveVBusDetIntOut(),
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.USBWireDataIn(USBWireDataIn),
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.USBWireDataInTick(),
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.USBWireDataOut(USBWireDataOut),
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.USBWireDataOutTick(),
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.USBWireCtrlOut(USBWireCtrlOut),
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.USBFullSpeed(USBFullSpeed),
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.USBDPlusPullup(usbDPlusPullup),
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.USBDMinusPullup(usbDMinusPullup),
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.vBusDetect(vBusDetect)
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);
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assign USBWireDataIn = {usbSlaveVP_in, usbSlaveVM_in};
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assign {usbSlaveVP_out, usbSlaveVM_out} = USBWireDataOut;
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assign usbSlaveOE_n = ~USBWireCtrlOut;
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checkLineState u_checkLineState (
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.clk(clk),
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.rst(rst),
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.initComplete(initComplete),
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.usbRstDet(usbRstDet),
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.wb_ack(wb_ack),
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.wb_addr(wb_addr0),
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.wb_data_i(wb_dat_from_usb),
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.wb_stb(wb_stb0),
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.wb_we(wb_we0),
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.wbBusGnt(wbBusGnt0),
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.wbBusReq(wbBusReq0)
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);
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EP0 u_EP0 (
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.clk(clk),
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.rst(rst | usbRstDet),
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.initComplete(initComplete),
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.wb_ack(wb_ack),
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.wb_addr(wb_addr1),
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.wb_data_i(wb_dat_from_usb),
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.wb_data_o(wb_data_o1),
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.wb_stb(wb_stb1),
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.wb_we(wb_we1),
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.wbBusGnt(wbBusGnt1),
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.wbBusReq(wbBusReq1),
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.memAddr(memAddr),
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.memData(memData),
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.memRdEn()
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);
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usbROM u_usbROM (
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.clk(clk),
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.addr(memAddr),
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.data(memData)
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);
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EP1Mouse u_EP1Mouse (
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.clk(clk),
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.rst(rst | usbRstDet),
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.initComplete(initComplete),
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.wb_ack(wb_ack),
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.wb_addr(wb_addr2),
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.wb_data_i(wb_dat_from_usb),
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.wb_data_o(wb_data_o2),
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.wb_stb(wb_stb2),
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.wb_we(wb_we2),
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.wbBusGnt(wbBusGnt2),
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.wbBusReq(wbBusReq2)
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);
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wishboneArb u_wishboneArb (
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.clk(clk),
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.rst(rst),
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.addr0_i(wb_addr0),
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.data0_i(8'h00),
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.stb0_i(wb_stb0),
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.we0_i(wb_we0),
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.req0(wbBusReq0),
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.gnt0(wbBusGnt0),
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.addr1_i(wb_addr1),
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.data1_i(wb_data_o1),
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.stb1_i(wb_stb1),
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.we1_i(wb_we1),
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.req1(wbBusReq1),
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.gnt1(wbBusGnt1),
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.addr2_i(wb_addr2),
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.data2_i(wb_data_o2),
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.stb2_i(wb_stb2),
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.we2_i(wb_we2),
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.req2(wbBusReq2),
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.gnt2(wbBusGnt2),
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.addr_o(wb_adr),
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.data_o(wb_dat_to_usb),
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.stb_o(wb_stb),
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.we_o(wb_we)
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);
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endmodule
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