repo2/common/components/usbhostslave/trunk/bench/testCase0.v
| 264 | markw | // ---------------------------------- testcase0.v ----------------------------
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`include "timescale.v"
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`include "usbHostSlave_h.v"
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`include "usbHostControl_h.v"
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`include "usbHostSlaveTB_defines.v"
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module testCase0();
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reg ack;
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reg [7:0] data;
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reg [15:0] dataWord;
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reg [7:0] dataRead;
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reg [7:0] dataWrite;
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reg [7:0] USBAddress;
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reg [7:0] USBEndPoint;
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reg [7:0] transType;
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integer dataSize;
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integer i;
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integer j;
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initial
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begin
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$write("\n\n");
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#1000;
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testHarness.u_wb_master_model.wb_read(1, `SIM_HOST_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_VERSION_REG , dataRead);
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$display("Host Version number = 0x%0x\n", dataRead);
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testHarness.u_wb_master_model.wb_read(1, `SIM_SLAVE_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_VERSION_REG , dataRead);
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$display("Slave Version number = 0x%0x\n", dataRead);
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$write("Testing host register read/write ");
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testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
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$write("--- PASSED\n");
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$write("Testing slave register read/write ");
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testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h70);
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h70);
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$write("--- PASSED\n");
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$write("Testing register reset ");
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testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG , 8'h2);
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testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG , 8'h2);
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#1000;
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h00);
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h00);
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$write("--- PASSED\n");
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#1000;
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$write("Configure host and slave mode. ");
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testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG , 8'h1);
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testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG , 8'h0);
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$write("Connect full speed ");
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testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
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testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h70);
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#20000;
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//expecting connection event interrupt
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
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//expecting full speed connect
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_CONNECT_STATE_REG , 6'h02);
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//expecting change in reset state event, and change in vbus state event
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h24);
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//expecting full speed connect and vbus present
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_LINE_STATUS_REG , 8'h06);
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$write("--- PASSED\n");
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$write("Cancel interrupts ");
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testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
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testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h24);
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//expecting all interrupts cancelled
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h00);
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//expecting all interrupts cancelled
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h00);
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$write("--- PASSED\n");
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#1000;
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$write("Disconnect ");
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testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
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testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h30);
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#10000;
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//expecting connection event interrupt
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
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//expecting disconnect state
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_CONNECT_STATE_REG , 8'h00);
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//expecting change in reset state event
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
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//expecting vbus present, and disconnect state
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_LINE_STATUS_REG , 8'h04);
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//cancel interrupts
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testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
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testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
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$write("--- PASSED\n");
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$write("Connect full speed ");
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testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
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testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h70);
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#20000;
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//expecting connection event interrupt
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
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//expecting full speed connect
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_CONNECT_STATE_REG , 8'h02);
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//expecting change in reset state event
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
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//expecting full speed connect and vbus present
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_LINE_STATUS_REG , 8'h06);
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//cancel interrupts
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testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
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testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h00);
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h00);
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$write("--- PASSED\n");
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#1000;
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$write("Host forcing reset ");
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testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h1c);
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#20000;
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//expecting change in reset state event
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
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//expecting vbus present, and disconnect state
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_LINE_STATUS_REG , 8'h04);
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//cancel interrupt
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testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
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$write("--- PASSED\n");
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$write("Connect full speed ");
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testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
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testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h70);
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#20000;
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//expecting no host interrupts
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h00);
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//expecting full speed connect
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_CONNECT_STATE_REG , 8'h02);
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//expecting change in reset state event
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
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//expecting full speed connect and vbus present
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_LINE_STATUS_REG , 8'h06);
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//cancel interrupts
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testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
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testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h00);
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h00);
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$write("--- PASSED\n");
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#1000;
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$write("Trans test: Device address = 0x00, 2 byte SETUP transaction to Endpoint 0. ");
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USBAddress = 8'h00;
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USBEndPoint = 8'h00;
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transType = `SETUP_TRANS;
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dataSize = 2;
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//enable endpoint, and make ready
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testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h71);
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testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_ADDRESS , USBAddress);
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testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`EP0_CTRL_REG , 8'h03);
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testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
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testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
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testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
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data = 8'h00;
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for (i=0; i<dataSize; i=i+1) begin
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testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , data);
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data = data + 1'b1;
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end
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testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
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#20000
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//expecting transaction done interrupt
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
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//expecting transaction done interrupt
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h01);
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//endpoint enabled, and endpoint ready cleared
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`EP0_CTRL_REG , 8'h01);
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$write("Checking receive data ");
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data = 8'h00;
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for (i=0; i<dataSize; i=i+1) begin
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `EP0_RX_FIFO_BASE + `FIFO_DATA_REG , data);
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data = data + 1'b1;
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end
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$write("--- PASSED\n");
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$write("Trans test: Device address = 0x5a, 20 byte OUT DATA0 transaction to Endpoint 1. ");
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USBAddress = 8'h5a;
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USBEndPoint = 8'h01;
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transType = `OUTDATA0_TRANS;
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dataSize = 20;
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//enable endpoint, and make ready
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testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h71);
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testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_ADDRESS , USBAddress);
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testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`EP1_CTRL_REG , 8'h03);
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testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
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testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
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testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
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data = 8'h00;
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for (i=0; i<dataSize; i=i+1) begin
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testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , data);
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data = data + 1'b1;
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end
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testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
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#20000
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//expecting transaction done interrupt
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
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//expecting transaction done interrupt
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h01);
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//endpoint enabled, and endpoint ready cleared
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`EP1_CTRL_REG , 8'h01);
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$write("Checking receive data ");
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data = 8'h00;
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for (i=0; i<dataSize; i=i+1) begin
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `EP1_RX_FIFO_BASE + `FIFO_DATA_REG , data);
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data = data + 1'b1;
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end
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$write("--- PASSED\n");
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$write("Trans test: Device address = 0x01, 2 byte IN transaction to Endpoint 2. ");
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USBAddress = 8'h01;
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USBEndPoint = 8'h02;
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transType = `IN_TRANS;
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dataSize = 2;
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//enable endpoint, and make ready
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testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h71);
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testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_ADDRESS , USBAddress);
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testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`EP2_CTRL_REG , 8'h03);
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testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
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testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
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testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
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data = 8'h00;
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for (i=0; i<dataSize; i=i+1) begin
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testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `EP2_TX_FIFO_BASE + `FIFO_DATA_REG , data);
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data = data + 1'b1;
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end
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testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
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#20000
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//expecting transaction done interrupt
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
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//expecting transaction done interrupt
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h01);
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//endpoint enabled, and endpoint ready cleared
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`EP2_CTRL_REG , 8'h01);
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$write("Checking receive data ");
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data = 8'h00;
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for (i=0; i<dataSize; i=i+1) begin
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testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_REG , data);
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data = data + 1'b1;
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end
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$write("--- PASSED\n");
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$write("Finished all tests\n");
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$stop;
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end
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endmodule
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