repo2/common/components/usbhostslave/trunk/RTL/wrapper/usbSlaveCyc2Wrap.v
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//// ////
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//// usbSlaveCyc2Wrap.v ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// Module Description: ////
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//// Top level module wrapper.
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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module usbSlaveCyc2Wrap(
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clk_i,
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rst_i,
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address_i,
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data_i,
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data_o,
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we_i,
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strobe_i,
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ack_o,
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irq,
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usbClk,
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USBWireVP,
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USBWireVM,
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USBWireOE_n,
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USBFullSpeed,
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USBDPlusPullup,
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USBDMinusPullup,
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vBusDetect
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);
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input clk_i;
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input rst_i;
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input [7:0] address_i;
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input [7:0] data_i;
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output [7:0] data_o;
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input we_i;
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input strobe_i;
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output ack_o;
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output irq;
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input usbClk;
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inout USBWireVP /* synthesis useioff=1 */;
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inout USBWireVM /* synthesis useioff=1 */;
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output USBWireOE_n /* synthesis useioff=1 */;
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output USBFullSpeed /* synthesis useioff=1 */;
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output USBDPlusPullup;
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output USBDMinusPullup;
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input vBusDetect;
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wire clk_i;
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wire rst_i;
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wire [7:0] address_i;
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wire [7:0] data_i;
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wire [7:0] data_o;
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wire irq;
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wire usbClk;
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wire USBWireDataOutTick;
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wire USBWireDataInTick;
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wire USBFullSpeed;
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//internal wiring
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wire slaveSOFRxedIntOut;
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wire slaveResetEventIntOut;
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wire slaveResumeIntOut;
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wire slaveTransDoneIntOut;
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wire slaveNAKSentIntOut;
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wire slaveVBusDetIntOut;
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wire USBWireCtrlOut;
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wire [1:0] USBWireDataIn;
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wire [1:0] USBWireDataOut;
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assign irq = slaveSOFRxedIntOut | slaveResetEventIntOut |
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slaveResumeIntOut | slaveTransDoneIntOut |
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slaveNAKSentIntOut | slaveVBusDetIntOut;
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assign USBWireDataIn = {USBWireVP, USBWireVM};
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assign {USBWireVP, USBWireVM} = (USBWireCtrlOut == 1'b1) ? USBWireDataOut : 2'bzz;
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assign USBWireOE_n = ~USBWireCtrlOut;
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//Parameters declaration:
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defparam usbSlaveInst.EP0_FIFO_DEPTH = 64;
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parameter EP0_FIFO_DEPTH = 64;
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defparam usbSlaveInst.EP0_FIFO_ADDR_WIDTH = 6;
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parameter EP0_FIFO_ADDR_WIDTH = 6;
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defparam usbSlaveInst.EP1_FIFO_DEPTH = 64;
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parameter EP1_FIFO_DEPTH = 64;
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defparam usbSlaveInst.EP1_FIFO_ADDR_WIDTH = 6;
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parameter EP1_FIFO_ADDR_WIDTH = 6;
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defparam usbSlaveInst.EP2_FIFO_DEPTH = 64;
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parameter EP2_FIFO_DEPTH = 64;
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defparam usbSlaveInst.EP2_FIFO_ADDR_WIDTH = 6;
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parameter EP2_FIFO_ADDR_WIDTH = 6;
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defparam usbSlaveInst.EP3_FIFO_DEPTH = 64;
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parameter EP3_FIFO_DEPTH = 64;
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defparam usbSlaveInst.EP3_FIFO_ADDR_WIDTH = 6;
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parameter EP3_FIFO_ADDR_WIDTH = 6;
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usbSlave usbSlaveInst (
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.clk_i(clk_i),
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.rst_i(rst_i),
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.address_i(address_i),
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.data_i(data_i),
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.data_o(data_o),
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.we_i(we_i),
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.strobe_i(strobe_i),
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.ack_o(ack_o),
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.usbClk(usbClk),
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.slaveSOFRxedIntOut(slaveSOFRxedIntOut),
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.slaveResetEventIntOut(slaveResetEventIntOut),
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.slaveResumeIntOut(slaveResumeIntOut),
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.slaveTransDoneIntOut(slaveTransDoneIntOut),
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.slaveNAKSentIntOut(slaveNAKSentIntOut),
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.slaveVBusDetIntOut(slaveVBusDetIntOut),
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.USBWireDataIn(USBWireDataIn),
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.USBWireDataInTick(USBWireDataInTick),
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.USBWireDataOut(USBWireDataOut),
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.USBWireDataOutTick(USBWireDataOutTick),
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.USBWireCtrlOut(USBWireCtrlOut),
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.USBFullSpeed(USBFullSpeed),
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.USBDPlusPullup(USBDPlusPullup),
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.USBDMinusPullup(USBDMinusPullup),
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.vBusDetect(vBusDetect)
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);
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endmodule
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