repo2/common/components/usbhostslave/trunk/RTL/wrapper/usbSlave.v
| 264 | markw | //////////////////////////////////////////////////////////////////////
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//// ////
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//// usbSlave.v ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// Module Description: ////
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//// Top level module
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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module usbSlave(
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clk_i,
|
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rst_i,
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address_i,
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data_i,
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data_o,
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we_i,
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strobe_i,
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ack_o,
|
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usbClk,
|
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slaveVBusDetIntOut,
|
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slaveNAKSentIntOut,
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slaveSOFRxedIntOut,
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slaveResetEventIntOut,
|
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slaveResumeIntOut,
|
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slaveTransDoneIntOut,
|
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USBWireDataIn,
|
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USBWireDataInTick,
|
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USBWireDataOut,
|
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USBWireDataOutTick,
|
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USBWireCtrlOut,
|
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USBFullSpeed,
|
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USBDPlusPullup,
|
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USBDMinusPullup,
|
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vBusDetect
|
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);
|
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parameter EP0_FIFO_DEPTH = 64;
|
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parameter EP0_FIFO_ADDR_WIDTH = 6;
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parameter EP1_FIFO_DEPTH = 64;
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parameter EP1_FIFO_ADDR_WIDTH = 6;
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parameter EP2_FIFO_DEPTH = 64;
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parameter EP2_FIFO_ADDR_WIDTH = 6;
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parameter EP3_FIFO_DEPTH = 64;
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parameter EP3_FIFO_ADDR_WIDTH = 6;
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input clk_i; //Wishbone bus clock. Maximum 5*usbClk=240MHz
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input rst_i; //Wishbone bus sync reset. Synchronous to 'clk_i'. Resets all logic
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input [7:0] address_i; //Wishbone bus address in
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input [7:0] data_i; //Wishbone bus data in
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output [7:0] data_o; //Wishbone bus data out
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input we_i; //Wishbone bus write enable in
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input strobe_i; //Wishbone bus strobe in
|
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output ack_o; //Wishbone bus acknowledge out
|
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input usbClk; //usb clock. 48Mhz +/-0.25%
|
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output slaveSOFRxedIntOut;
|
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output slaveResetEventIntOut;
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output slaveResumeIntOut;
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output slaveTransDoneIntOut;
|
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output slaveNAKSentIntOut;
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output slaveVBusDetIntOut;
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input [1:0] USBWireDataIn;
|
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output [1:0] USBWireDataOut;
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output USBWireDataOutTick;
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output USBWireDataInTick;
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output USBWireCtrlOut;
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output USBFullSpeed;
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output USBDPlusPullup;
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output USBDMinusPullup;
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input vBusDetect;
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wire clk_i;
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wire rst_i;
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wire [7:0] address_i;
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wire [7:0] data_i;
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wire [7:0] data_o;
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wire we_i;
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wire strobe_i;
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wire ack_o;
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wire usbClk;
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wire slaveSOFRxedIntOut;
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wire slaveResetEventIntOut;
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wire slaveResumeIntOut;
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wire slaveTransDoneIntOut;
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wire slaveNAKSentIntOut;
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wire slaveVBusDetIntOut;
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wire [1:0] USBWireDataIn;
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wire [1:0] USBWireDataOut;
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wire USBWireDataOutTick;
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wire USBWireDataInTick;
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wire USBWireCtrlOut;
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wire USBFullSpeed;
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wire USBDPlusPullup;
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wire USBDMinusPullup;
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wire vBusDetect;
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//internal wiring
|
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wire slaveControlSel;
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wire hostSlaveMuxSel;
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wire [7:0] dataFromSlaveControl;
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wire [7:0] dataFromHostSlaveMux;
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wire [7:0] RxCtrlOut;
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wire [7:0] RxDataFromSIE;
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wire RxDataOutWEn;
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wire fullSpeedBitRateFromSlave;
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wire fullSpeedPolarityFromSlave;
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wire SIEPortWEnFromSlave;
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wire SIEPortTxRdy;
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wire [7:0] SIEPortDataInFromSlave;
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wire [7:0] SIEPortCtrlInFromSlave;
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wire [1:0] connectState;
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wire resumeDetected;
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wire [7:0] SIEPortDataInToSIE;
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wire SIEPortWEnToSIE;
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wire [7:0] SIEPortCtrlInToSIE;
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wire fullSpeedPolarityToSIE;
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wire fullSpeedBitRateToSIE;
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wire connectSlaveToHost;
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wire noActivityTimeOut;
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wire TxFifoEP0REn;
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wire TxFifoEP1REn;
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wire TxFifoEP2REn;
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wire TxFifoEP3REn;
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wire [7:0] TxFifoEP0Data;
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wire [7:0] TxFifoEP1Data;
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wire [7:0] TxFifoEP2Data;
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wire [7:0] TxFifoEP3Data;
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wire TxFifoEP0Empty;
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wire TxFifoEP1Empty;
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wire TxFifoEP2Empty;
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wire TxFifoEP3Empty;
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wire RxFifoEP0WEn;
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wire RxFifoEP1WEn;
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wire RxFifoEP2WEn;
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wire RxFifoEP3WEn;
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wire RxFifoEP0Full;
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wire RxFifoEP1Full;
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wire RxFifoEP2Full;
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wire RxFifoEP3Full;
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wire [7:0] slaveRxFifoData;
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wire [7:0] dataFromEP0RxFifo;
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wire [7:0] dataFromEP1RxFifo;
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wire [7:0] dataFromEP2RxFifo;
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wire [7:0] dataFromEP3RxFifo;
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wire [7:0] dataFromEP0TxFifo;
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wire [7:0] dataFromEP1TxFifo;
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wire [7:0] dataFromEP2TxFifo;
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wire [7:0] dataFromEP3TxFifo;
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wire slaveEP0RxFifoSel;
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wire slaveEP1RxFifoSel;
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wire slaveEP2RxFifoSel;
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wire slaveEP3RxFifoSel;
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wire slaveEP0TxFifoSel;
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wire slaveEP1TxFifoSel;
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wire slaveEP2TxFifoSel;
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wire slaveEP3TxFifoSel;
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wire rstSyncToBusClk;
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wire rstSyncToUsbClk;
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wire noActivityTimeOutEnableToSIE;
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wire noActivityTimeOutEnableFromHost;
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wire noActivityTimeOutEnableFromSlave;
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// This is not a bug.
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// USBFullSpeed controls the PHY edge speed.
|
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// The only time that the PHY needs to operate with low speed edge rate is
|
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// when the host is directly connected to a low speed device. And when this is true, fullSpeedPolarity
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// will be low. When the host is connected to a low speed device via a hub, then speed can be full or low
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// but according to spec edge speed must be full rate edge speed.
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assign USBFullSpeed = fullSpeedPolarityToSIE;
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//assign USBFullSpeed = fullSpeedBitRateToSIE;
|
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assign USBDPlusPullup = (USBFullSpeed & connectSlaveToHost);
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assign USBDMinusPullup = (~USBFullSpeed & connectSlaveToHost);
|
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usbSlaveControl u_usbSlaveControl(
|
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.busClk(clk_i),
|
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.rstSyncToBusClk(rstSyncToBusClk),
|
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.usbClk(usbClk),
|
|||
.rstSyncToUsbClk(rstSyncToUsbClk),
|
|||
.RxByteStatus(RxCtrlOut),
|
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.RxData(RxDataFromSIE),
|
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.RxDataValid(RxDataOutWEn),
|
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.SIERxTimeOut(noActivityTimeOut),
|
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.SIERxTimeOutEn(noActivityTimeOutEnableFromSlave),
|
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.RxFifoData(slaveRxFifoData),
|
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.connectSlaveToHost(connectSlaveToHost),
|
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.fullSpeedRate(fullSpeedBitRateFromSlave),
|
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.fullSpeedPol(fullSpeedPolarityFromSlave),
|
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.SCTxPortEn(SIEPortWEnFromSlave),
|
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.SCTxPortRdy(SIEPortTxRdy),
|
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.SCTxPortData(SIEPortDataInFromSlave),
|
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.SCTxPortCtrl(SIEPortCtrlInFromSlave),
|
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.vBusDetect(vBusDetect),
|
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.connectStateIn(connectState),
|
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.resumeDetectedIn(resumeDetected),
|
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.busAddress(address_i[4:0]),
|
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.busDataIn(data_i),
|
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.busDataOut(dataFromSlaveControl),
|
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.busWriteEn(we_i),
|
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.busStrobe_i(strobe_i),
|
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.SOFRxedIntOut(slaveSOFRxedIntOut),
|
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.resetEventIntOut(slaveResetEventIntOut),
|
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.resumeIntOut(slaveResumeIntOut),
|
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.transDoneIntOut(slaveTransDoneIntOut),
|
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.NAKSentIntOut(slaveNAKSentIntOut),
|
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.vBusDetIntOut(slaveVBusDetIntOut),
|
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.slaveControlSelect(slaveControlSel),
|
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.TxFifoEP0REn(TxFifoEP0REn),
|
|||
.TxFifoEP1REn(TxFifoEP1REn),
|
|||
.TxFifoEP2REn(TxFifoEP2REn),
|
|||
.TxFifoEP3REn(TxFifoEP3REn),
|
|||
.TxFifoEP0Data(TxFifoEP0Data),
|
|||
.TxFifoEP1Data(TxFifoEP1Data),
|
|||
.TxFifoEP2Data(TxFifoEP2Data),
|
|||
.TxFifoEP3Data(TxFifoEP3Data),
|
|||
.TxFifoEP0Empty(TxFifoEP0Empty),
|
|||
.TxFifoEP1Empty(TxFifoEP1Empty),
|
|||
.TxFifoEP2Empty(TxFifoEP2Empty),
|
|||
.TxFifoEP3Empty(TxFifoEP3Empty),
|
|||
.RxFifoEP0WEn(RxFifoEP0WEn),
|
|||
.RxFifoEP1WEn(RxFifoEP1WEn),
|
|||
.RxFifoEP2WEn(RxFifoEP2WEn),
|
|||
.RxFifoEP3WEn(RxFifoEP3WEn),
|
|||
.RxFifoEP0Full(RxFifoEP0Full),
|
|||
.RxFifoEP1Full(RxFifoEP1Full),
|
|||
.RxFifoEP2Full(RxFifoEP2Full),
|
|||
.RxFifoEP3Full(RxFifoEP3Full)
|
|||
);
|
|||
wishBoneBI u_wishBoneBI (
|
|||
.address(address_i),
|
|||
.dataIn(data_i),
|
|||
.dataOut(data_o),
|
|||
.writeEn(we_i),
|
|||
.strobe_i(strobe_i),
|
|||
.ack_o(ack_o),
|
|||
.clk(clk_i),
|
|||
.rst(rstSyncToBusClk),
|
|||
.hostControlSel(),
|
|||
.hostRxFifoSel(),
|
|||
.hostTxFifoSel(),
|
|||
.slaveControlSel(slaveControlSel),
|
|||
.slaveEP0RxFifoSel(slaveEP0RxFifoSel),
|
|||
.slaveEP1RxFifoSel(slaveEP1RxFifoSel),
|
|||
.slaveEP2RxFifoSel(slaveEP2RxFifoSel),
|
|||
.slaveEP3RxFifoSel(slaveEP3RxFifoSel),
|
|||
.slaveEP0TxFifoSel(slaveEP0TxFifoSel),
|
|||
.slaveEP1TxFifoSel(slaveEP1TxFifoSel),
|
|||
.slaveEP2TxFifoSel(slaveEP2TxFifoSel),
|
|||
.slaveEP3TxFifoSel(slaveEP3TxFifoSel),
|
|||
.hostSlaveMuxSel(hostSlaveMuxSel),
|
|||
.dataFromHostControl(8'h00),
|
|||
.dataFromHostRxFifo(8'h00),
|
|||
.dataFromHostTxFifo(8'h00),
|
|||
.dataFromSlaveControl(dataFromSlaveControl),
|
|||
.dataFromEP0RxFifo(dataFromEP0RxFifo),
|
|||
.dataFromEP1RxFifo(dataFromEP1RxFifo),
|
|||
.dataFromEP2RxFifo(dataFromEP2RxFifo),
|
|||
.dataFromEP3RxFifo(dataFromEP3RxFifo),
|
|||
.dataFromEP0TxFifo(dataFromEP0TxFifo),
|
|||
.dataFromEP1TxFifo(dataFromEP1TxFifo),
|
|||
.dataFromEP2TxFifo(dataFromEP2TxFifo),
|
|||
.dataFromEP3TxFifo(dataFromEP3TxFifo),
|
|||
.dataFromHostSlaveMux(dataFromHostSlaveMux)
|
|||
);
|
|||
assign SIEPortCtrlInToSIE = SIEPortCtrlInFromSlave;
|
|||
assign SIEPortDataInToSIE = SIEPortDataInFromSlave;
|
|||
assign SIEPortWEnToSIE = SIEPortWEnFromSlave;
|
|||
assign fullSpeedPolarityToSIE = fullSpeedPolarityFromSlave;
|
|||
assign fullSpeedBitRateToSIE = fullSpeedBitRateFromSlave;
|
|||
assign noActivityTimeOutEnableToSIE = noActivityTimeOutEnableFromSlave;
|
|||
hostSlaveMuxBI u_hostSlaveMuxBI (
|
|||
.dataIn(data_i),
|
|||
.dataOut(dataFromHostSlaveMux),
|
|||
.address(address_i[0]),
|
|||
.writeEn(we_i),
|
|||
.strobe_i(strobe_i),
|
|||
.usbClk(usbClk),
|
|||
.busClk(clk_i),
|
|||
.hostSlaveMuxSel(hostSlaveMuxSel),
|
|||
.hostMode(),
|
|||
.rstFromWire(rst_i),
|
|||
.rstSyncToBusClkOut(rstSyncToBusClk),
|
|||
.rstSyncToUsbClkOut(rstSyncToUsbClk)
|
|||
);
|
|||
usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
|
|||
.clk(usbClk),
|
|||
.rst(rstSyncToUsbClk),
|
|||
.USBWireDataIn(USBWireDataIn),
|
|||
.USBWireDataOut(USBWireDataOut),
|
|||
.USBWireDataInTick(USBWireDataInTick),
|
|||
.USBWireDataOutTick(USBWireDataOutTick),
|
|||
.USBWireCtrlOut(USBWireCtrlOut),
|
|||
.connectState(connectState),
|
|||
.resumeDetected(resumeDetected),
|
|||
.RxCtrlOut(RxCtrlOut),
|
|||
.RxDataOutWEn(RxDataOutWEn),
|
|||
.RxDataOut(RxDataFromSIE),
|
|||
.SIEPortCtrlIn(SIEPortCtrlInToSIE),
|
|||
.SIEPortDataIn(SIEPortDataInToSIE),
|
|||
.SIEPortTxRdy(SIEPortTxRdy),
|
|||
.SIEPortWEn(SIEPortWEnToSIE),
|
|||
.fullSpeedPolarity(fullSpeedPolarityToSIE),
|
|||
.fullSpeedBitRate(fullSpeedBitRateToSIE),
|
|||
.noActivityTimeOut(noActivityTimeOut),
|
|||
.noActivityTimeOutEnable(noActivityTimeOutEnableToSIE)
|
|||
);
|
|||
//---Slave fifos
|
|||
TxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0TxFifo (
|
|||
.usbClk(usbClk),
|
|||
.busClk(clk_i),
|
|||
.rstSyncToBusClk(rstSyncToBusClk),
|
|||
.rstSyncToUsbClk(rstSyncToUsbClk),
|
|||
.fifoREn(TxFifoEP0REn),
|
|||
.fifoEmpty(TxFifoEP0Empty),
|
|||
.busAddress(address_i[2:0]),
|
|||
.busWriteEn(we_i),
|
|||
.busStrobe_i(strobe_i),
|
|||
.busFifoSelect(slaveEP0TxFifoSel),
|
|||
.busDataIn(data_i),
|
|||
.busDataOut(dataFromEP0TxFifo),
|
|||
.fifoDataOut(TxFifoEP0Data) );
|
|||
TxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1TxFifo (
|
|||
.usbClk(usbClk),
|
|||
.busClk(clk_i),
|
|||
.rstSyncToBusClk(rstSyncToBusClk),
|
|||
.rstSyncToUsbClk(rstSyncToUsbClk),
|
|||
.fifoREn(TxFifoEP1REn),
|
|||
.fifoEmpty(TxFifoEP1Empty),
|
|||
.busAddress(address_i[2:0]),
|
|||
.busWriteEn(we_i),
|
|||
.busStrobe_i(strobe_i),
|
|||
.busFifoSelect(slaveEP1TxFifoSel),
|
|||
.busDataIn(data_i),
|
|||
.busDataOut(dataFromEP1TxFifo),
|
|||
.fifoDataOut(TxFifoEP1Data) );
|
|||
TxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2TxFifo (
|
|||
.usbClk(usbClk),
|
|||
.busClk(clk_i),
|
|||
.rstSyncToBusClk(rstSyncToBusClk),
|
|||
.rstSyncToUsbClk(rstSyncToUsbClk),
|
|||
.fifoREn(TxFifoEP2REn),
|
|||
.fifoEmpty(TxFifoEP2Empty),
|
|||
.busAddress(address_i[2:0]),
|
|||
.busWriteEn(we_i),
|
|||
.busStrobe_i(strobe_i),
|
|||
.busFifoSelect(slaveEP2TxFifoSel),
|
|||
.busDataIn(data_i),
|
|||
.busDataOut(dataFromEP2TxFifo),
|
|||
.fifoDataOut(TxFifoEP2Data) );
|
|||
TxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3TxFifo (
|
|||
.usbClk(usbClk),
|
|||
.busClk(clk_i),
|
|||
.rstSyncToBusClk(rstSyncToBusClk),
|
|||
.rstSyncToUsbClk(rstSyncToUsbClk),
|
|||
.fifoREn(TxFifoEP3REn),
|
|||
.fifoEmpty(TxFifoEP3Empty),
|
|||
.busAddress(address_i[2:0]),
|
|||
.busWriteEn(we_i),
|
|||
.busStrobe_i(strobe_i),
|
|||
.busFifoSelect(slaveEP3TxFifoSel),
|
|||
.busDataIn(data_i),
|
|||
.busDataOut(dataFromEP3TxFifo),
|
|||
.fifoDataOut(TxFifoEP3Data) );
|
|||
RxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0RxFifo(
|
|||
.usbClk(usbClk),
|
|||
.busClk(clk_i),
|
|||
.rstSyncToBusClk(rstSyncToBusClk),
|
|||
.rstSyncToUsbClk(rstSyncToUsbClk),
|
|||
.fifoWEn(RxFifoEP0WEn),
|
|||
.fifoFull(RxFifoEP0Full),
|
|||
.busAddress(address_i[2:0]),
|
|||
.busWriteEn(we_i),
|
|||
.busStrobe_i(strobe_i),
|
|||
.busFifoSelect(slaveEP0RxFifoSel),
|
|||
.busDataIn(data_i),
|
|||
.busDataOut(dataFromEP0RxFifo),
|
|||
.fifoDataIn(slaveRxFifoData) );
|
|||
RxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1RxFifo(
|
|||
.usbClk(usbClk),
|
|||
.busClk(clk_i),
|
|||
.rstSyncToBusClk(rstSyncToBusClk),
|
|||
.rstSyncToUsbClk(rstSyncToUsbClk),
|
|||
.fifoWEn(RxFifoEP1WEn),
|
|||
.fifoFull(RxFifoEP1Full),
|
|||
.busAddress(address_i[2:0]),
|
|||
.busWriteEn(we_i),
|
|||
.busStrobe_i(strobe_i),
|
|||
.busFifoSelect(slaveEP1RxFifoSel),
|
|||
.busDataIn(data_i),
|
|||
.busDataOut(dataFromEP1RxFifo),
|
|||
.fifoDataIn(slaveRxFifoData) );
|
|||
RxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2RxFifo(
|
|||
.usbClk(usbClk),
|
|||
.busClk(clk_i),
|
|||
.rstSyncToBusClk(rstSyncToBusClk),
|
|||
.rstSyncToUsbClk(rstSyncToUsbClk),
|
|||
.fifoWEn(RxFifoEP2WEn),
|
|||
.fifoFull(RxFifoEP2Full),
|
|||
.busAddress(address_i[2:0]),
|
|||
.busWriteEn(we_i),
|
|||
.busStrobe_i(strobe_i),
|
|||
.busFifoSelect(slaveEP2RxFifoSel),
|
|||
.busDataIn(data_i),
|
|||
.busDataOut(dataFromEP2RxFifo),
|
|||
.fifoDataIn(slaveRxFifoData) );
|
|||
RxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3RxFifo(
|
|||
.usbClk(usbClk),
|
|||
.busClk(clk_i),
|
|||
.rstSyncToBusClk(rstSyncToBusClk),
|
|||
.rstSyncToUsbClk(rstSyncToUsbClk),
|
|||
.fifoWEn(RxFifoEP3WEn),
|
|||
.fifoFull(RxFifoEP3Full),
|
|||
.busAddress(address_i[2:0]),
|
|||
.busWriteEn(we_i),
|
|||
.busStrobe_i(strobe_i),
|
|||
.busFifoSelect(slaveEP3RxFifoSel),
|
|||
.busDataIn(data_i),
|
|||
.busDataOut(dataFromEP3RxFifo),
|
|||
.fifoDataIn(slaveRxFifoData) );
|
|||
endmodule
|
|||