repo2/common/components/usbhostslave/trunk/RTL/wrapper/usbHost.v
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//// ////
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//// usbHost.v ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// Module Description: ////
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//// Top level module
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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module usbHost(
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clk_i,
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rst_i,
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address_i,
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data_i,
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data_o,
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we_i,
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strobe_i,
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ack_o,
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usbClk,
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hostSOFSentIntOut,
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hostConnEventIntOut,
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hostResumeIntOut,
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hostTransDoneIntOut,
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USBWireDataIn,
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USBWireDataInTick,
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USBWireDataOut,
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USBWireDataOutTick,
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USBWireCtrlOut,
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USBFullSpeed
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);
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parameter HOST_FIFO_DEPTH = 64; //HOST_FIFO_DEPTH = 2^HOST_ADDR_WIDTH
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parameter HOST_FIFO_ADDR_WIDTH = 6;
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input clk_i; //Wishbone bus clock. Maximum 5*usbClk=240MHz
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input rst_i; //Wishbone bus sync reset. Synchronous to 'clk_i'. Resets all logic
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input [7:0] address_i; //Wishbone bus address in
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input [7:0] data_i; //Wishbone bus data in
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output [7:0] data_o; //Wishbone bus data out
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input we_i; //Wishbone bus write enable in
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input strobe_i; //Wishbone bus strobe in
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output ack_o; //Wishbone bus acknowledge out
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input usbClk; //usb clock. 48Mhz +/-0.25%
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output hostSOFSentIntOut;
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output hostConnEventIntOut;
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output hostResumeIntOut;
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output hostTransDoneIntOut;
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input [1:0] USBWireDataIn;
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output [1:0] USBWireDataOut;
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output USBWireDataOutTick;
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output USBWireDataInTick;
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output USBWireCtrlOut;
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output USBFullSpeed;
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wire clk_i;
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wire rst_i;
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wire [7:0] address_i;
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wire [7:0] data_i;
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wire [7:0] data_o;
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wire we_i;
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wire strobe_i;
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wire ack_o;
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wire usbClk;
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wire hostSOFSentIntOut;
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wire hostConnEventIntOut;
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wire hostResumeIntOut;
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wire hostTransDoneIntOut;
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wire [1:0] USBWireDataIn;
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wire [1:0] USBWireDataOut;
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wire USBWireDataOutTick;
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wire USBWireDataInTick;
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wire USBWireCtrlOut;
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wire USBFullSpeed;
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//internal wiring
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wire hostControlSel;
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wire slaveControlSel;
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wire hostRxFifoSel;
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wire hostTxFifoSel;
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wire hostSlaveMuxSel;
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wire [7:0] dataFromHostControl;
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wire [7:0] dataFromSlaveControl;
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wire [7:0] dataFromHostRxFifo;
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wire [7:0] dataFromHostTxFifo;
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wire [7:0] dataFromHostSlaveMux;
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wire hostTxFifoRE;
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wire [7:0] hostTxFifoData;
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wire hostTxFifoEmpty;
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wire hostRxFifoWE;
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wire [7:0] hostRxFifoData;
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wire hostRxFifoFull;
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wire [7:0] RxCtrlOut;
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wire [7:0] RxDataFromSIE;
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wire RxDataOutWEn;
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wire fullSpeedBitRateFromHost;
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wire fullSpeedPolarityFromHost;
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wire SIEPortWEnFromHost;
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wire SIEPortTxRdy;
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wire [7:0] SIEPortDataInFromHost;
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wire [7:0] SIEPortCtrlInFromHost;
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wire [1:0] connectState;
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wire resumeDetected;
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wire [7:0] SIEPortDataInToSIE;
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wire SIEPortWEnToSIE;
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wire [7:0] SIEPortCtrlInToSIE;
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wire fullSpeedPolarityToSIE;
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wire fullSpeedBitRateToSIE;
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wire noActivityTimeOut;
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wire rstSyncToBusClk;
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wire rstSyncToUsbClk;
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wire noActivityTimeOutEnableToSIE;
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wire noActivityTimeOutEnableFromHost;
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// This is not a bug.
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// USBFullSpeed controls the PHY edge speed.
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// The only time that the PHY needs to operate with low speed edge rate is
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// when the host is directly connected to a low speed device. And when this is true, fullSpeedPolarity
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// will be low. When the host is connected to a low speed device via a hub, then speed can be full or low
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// but according to spec edge speed must be full rate edge speed.
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assign USBFullSpeed = fullSpeedPolarityToSIE;
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//assign USBFullSpeed = fullSpeedBitRateToSIE;
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usbHostControl u_usbHostControl(
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.busClk(clk_i),
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.rstSyncToBusClk(rstSyncToBusClk),
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.usbClk(usbClk),
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.rstSyncToUsbClk(rstSyncToUsbClk),
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.TxFifoRE(hostTxFifoRE),
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.TxFifoData(hostTxFifoData),
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.TxFifoEmpty(hostTxFifoEmpty),
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.RxFifoWE(hostRxFifoWE),
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.RxFifoData(hostRxFifoData),
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.RxFifoFull(hostRxFifoFull),
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.RxByteStatus(RxCtrlOut),
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.RxData(RxDataFromSIE),
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.RxDataValid(RxDataOutWEn),
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.SIERxTimeOut(noActivityTimeOut),
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.SIERxTimeOutEn(noActivityTimeOutEnableFromHost),
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.fullSpeedRate(fullSpeedBitRateFromHost),
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.fullSpeedPol(fullSpeedPolarityFromHost),
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.HCTxPortEn(SIEPortWEnFromHost),
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.HCTxPortRdy(SIEPortTxRdy),
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.HCTxPortData(SIEPortDataInFromHost),
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.HCTxPortCtrl(SIEPortCtrlInFromHost),
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.connectStateIn(connectState),
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.resumeDetectedIn(resumeDetected),
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.busAddress(address_i[3:0]),
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.busDataIn(data_i),
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.busDataOut(dataFromHostControl),
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.busWriteEn(we_i),
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.busStrobe_i(strobe_i),
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.SOFSentIntOut(hostSOFSentIntOut),
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.connEventIntOut(hostConnEventIntOut),
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.resumeIntOut(hostResumeIntOut),
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.transDoneIntOut(hostTransDoneIntOut),
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.hostControlSelect(hostControlSel) );
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wishBoneBI u_wishBoneBI (
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.address(address_i),
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.dataIn(data_i),
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.dataOut(data_o),
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.writeEn(we_i),
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.strobe_i(strobe_i),
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.ack_o(ack_o),
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.clk(clk_i),
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.rst(rstSyncToBusClk),
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.hostControlSel(hostControlSel),
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.hostRxFifoSel(hostRxFifoSel),
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.hostTxFifoSel(hostTxFifoSel),
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.slaveControlSel(),
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.slaveEP0RxFifoSel(),
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.slaveEP1RxFifoSel(),
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.slaveEP2RxFifoSel(),
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.slaveEP3RxFifoSel(),
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.slaveEP0TxFifoSel(),
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.slaveEP1TxFifoSel(),
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.slaveEP2TxFifoSel(),
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.slaveEP3TxFifoSel(),
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.hostSlaveMuxSel(hostSlaveMuxSel),
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.dataFromHostControl(dataFromHostControl),
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.dataFromHostRxFifo(dataFromHostRxFifo),
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.dataFromHostTxFifo(dataFromHostTxFifo),
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.dataFromSlaveControl(8'h00),
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.dataFromEP0RxFifo(8'h00),
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.dataFromEP1RxFifo(8'h00),
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.dataFromEP2RxFifo(8'h00),
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.dataFromEP3RxFifo(8'h00),
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.dataFromEP0TxFifo(8'h00),
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.dataFromEP1TxFifo(8'h00),
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.dataFromEP2TxFifo(8'h00),
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.dataFromEP3TxFifo(8'h00),
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.dataFromHostSlaveMux(dataFromHostSlaveMux)
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);
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assign SIEPortCtrlInToSIE = SIEPortCtrlInFromHost;
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assign SIEPortDataInToSIE = SIEPortDataInFromHost;
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assign SIEPortWEnToSIE = SIEPortWEnFromHost;
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assign fullSpeedPolarityToSIE = fullSpeedPolarityFromHost;
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assign fullSpeedBitRateToSIE = fullSpeedBitRateFromHost;
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assign noActivityTimeOutEnableToSIE = noActivityTimeOutEnableFromHost;
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hostSlaveMuxBI u_hostSlaveMuxBI (
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.dataIn(data_i),
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.dataOut(dataFromHostSlaveMux),
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.address(address_i[0]),
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.writeEn(we_i),
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.strobe_i(strobe_i),
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.usbClk(usbClk),
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.busClk(clk_i),
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.hostMode(hostMode),
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.hostSlaveMuxSel(hostSlaveMuxSel),
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.rstFromWire(rst_i),
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.rstSyncToBusClkOut(rstSyncToBusClk),
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.rstSyncToUsbClkOut(rstSyncToUsbClk)
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);
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usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
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.clk(usbClk),
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.rst(rstSyncToUsbClk),
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.USBWireDataIn(USBWireDataIn),
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.USBWireDataOut(USBWireDataOut),
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.USBWireDataInTick(USBWireDataInTick),
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.USBWireDataOutTick(USBWireDataOutTick),
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.USBWireCtrlOut(USBWireCtrlOut),
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.connectState(connectState),
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.resumeDetected(resumeDetected),
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.RxCtrlOut(RxCtrlOut),
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.RxDataOutWEn(RxDataOutWEn),
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.RxDataOut(RxDataFromSIE),
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.SIEPortCtrlIn(SIEPortCtrlInToSIE),
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.SIEPortDataIn(SIEPortDataInToSIE),
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.SIEPortTxRdy(SIEPortTxRdy),
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.SIEPortWEn(SIEPortWEnToSIE),
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.fullSpeedPolarity(fullSpeedPolarityToSIE),
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.fullSpeedBitRate(fullSpeedBitRateToSIE),
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.noActivityTimeOut(noActivityTimeOut),
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.noActivityTimeOutEnable(noActivityTimeOutEnableToSIE)
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);
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//---Host fifos
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TxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostTxFifo (
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.usbClk(usbClk),
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.busClk(clk_i),
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.rstSyncToBusClk(rstSyncToBusClk),
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.rstSyncToUsbClk(rstSyncToUsbClk),
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.fifoREn(hostTxFifoRE),
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.fifoEmpty(hostTxFifoEmpty),
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.busAddress(address_i[2:0]),
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.busWriteEn(we_i),
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.busStrobe_i(strobe_i),
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.busFifoSelect(hostTxFifoSel),
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.busDataIn(data_i),
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.busDataOut(dataFromHostTxFifo),
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.fifoDataOut(hostTxFifoData) );
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RxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostRxFifo(
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.usbClk(usbClk),
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.busClk(clk_i),
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.rstSyncToBusClk(rstSyncToBusClk),
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.rstSyncToUsbClk(rstSyncToUsbClk),
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.fifoWEn(hostRxFifoWE),
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.fifoFull(hostRxFifoFull),
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.busAddress(address_i[2:0]),
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.busWriteEn(we_i),
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.busStrobe_i(strobe_i),
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.busFifoSelect(hostRxFifoSel),
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.busDataIn(data_i),
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.busDataOut(dataFromHostRxFifo),
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.fifoDataIn(hostRxFifoData) );
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endmodule
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