repo2/common/components/usbhostslave/trunk/RTL/slaveController/fifoMux.v
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//// ////
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//// fifoMux.v ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// Module Description: ////
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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module fifoMux (
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currEndP,
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//TxFifo
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TxFifoREn,
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TxFifoEP0REn,
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TxFifoEP1REn,
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TxFifoEP2REn,
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TxFifoEP3REn,
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TxFifoData,
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TxFifoEP0Data,
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TxFifoEP1Data,
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TxFifoEP2Data,
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TxFifoEP3Data,
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TxFifoEmpty,
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TxFifoEP0Empty,
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TxFifoEP1Empty,
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TxFifoEP2Empty,
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TxFifoEP3Empty,
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//RxFifo
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RxFifoWEn,
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RxFifoEP0WEn,
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RxFifoEP1WEn,
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RxFifoEP2WEn,
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RxFifoEP3WEn,
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RxFifoFull,
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RxFifoEP0Full,
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RxFifoEP1Full,
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RxFifoEP2Full,
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RxFifoEP3Full
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);
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input [3:0] currEndP;
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//TxFifo
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input TxFifoREn;
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output TxFifoEP0REn;
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output TxFifoEP1REn;
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output TxFifoEP2REn;
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output TxFifoEP3REn;
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output [7:0] TxFifoData;
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input [7:0] TxFifoEP0Data;
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input [7:0] TxFifoEP1Data;
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input [7:0] TxFifoEP2Data;
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input [7:0] TxFifoEP3Data;
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output TxFifoEmpty;
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input TxFifoEP0Empty;
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input TxFifoEP1Empty;
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input TxFifoEP2Empty;
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input TxFifoEP3Empty;
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//RxFifo
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input RxFifoWEn;
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output RxFifoEP0WEn;
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output RxFifoEP1WEn;
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output RxFifoEP2WEn;
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output RxFifoEP3WEn;
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output RxFifoFull;
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input RxFifoEP0Full;
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input RxFifoEP1Full;
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input RxFifoEP2Full;
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input RxFifoEP3Full;
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wire [3:0] currEndP;
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//TxFifo
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wire TxFifoREn;
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reg TxFifoEP0REn;
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reg TxFifoEP1REn;
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reg TxFifoEP2REn;
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reg TxFifoEP3REn;
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reg [7:0] TxFifoData;
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wire [7:0] TxFifoEP0Data;
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wire [7:0] TxFifoEP1Data;
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wire [7:0] TxFifoEP2Data;
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wire [7:0] TxFifoEP3Data;
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reg TxFifoEmpty;
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wire TxFifoEP0Empty;
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wire TxFifoEP1Empty;
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wire TxFifoEP2Empty;
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wire TxFifoEP3Empty;
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//RxFifo
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wire RxFifoWEn;
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reg RxFifoEP0WEn;
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reg RxFifoEP1WEn;
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reg RxFifoEP2WEn;
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reg RxFifoEP3WEn;
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reg RxFifoFull;
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wire RxFifoEP0Full;
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wire RxFifoEP1Full;
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wire RxFifoEP2Full;
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wire RxFifoEP3Full;
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//internal wires and regs
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//combinatorially mux TX and RX fifos for end points 0 through 3
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always @(currEndP or
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TxFifoREn or
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RxFifoWEn or
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TxFifoEP0Data or
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TxFifoEP1Data or
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TxFifoEP2Data or
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TxFifoEP3Data or
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TxFifoEP0Empty or
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TxFifoEP1Empty or
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TxFifoEP2Empty or
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TxFifoEP3Empty or
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RxFifoEP0Full or
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RxFifoEP1Full or
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RxFifoEP2Full or
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RxFifoEP3Full)
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begin
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case (currEndP[1:0])
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2'b00: begin
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TxFifoEP0REn <= TxFifoREn;
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TxFifoEP1REn <= 1'b0;
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TxFifoEP2REn <= 1'b0;
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TxFifoEP3REn <= 1'b0;
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TxFifoData <= TxFifoEP0Data;
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TxFifoEmpty <= TxFifoEP0Empty;
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RxFifoEP0WEn <= RxFifoWEn;
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RxFifoEP1WEn <= 1'b0;
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RxFifoEP2WEn <= 1'b0;
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RxFifoEP3WEn <= 1'b0;
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RxFifoFull <= RxFifoEP0Full;
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end
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2'b01: begin
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TxFifoEP0REn <= 1'b0;
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TxFifoEP1REn <= TxFifoREn;
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TxFifoEP2REn <= 1'b0;
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TxFifoEP3REn <= 1'b0;
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TxFifoData <= TxFifoEP1Data;
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TxFifoEmpty <= TxFifoEP1Empty;
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RxFifoEP0WEn <= 1'b0;
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RxFifoEP1WEn <= RxFifoWEn;
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RxFifoEP2WEn <= 1'b0;
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RxFifoEP3WEn <= 1'b0;
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RxFifoFull <= RxFifoEP1Full;
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end
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2'b10: begin
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TxFifoEP0REn <= 1'b0;
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TxFifoEP1REn <= 1'b0;
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TxFifoEP2REn <= TxFifoREn;
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TxFifoEP3REn <= 1'b0;
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TxFifoData <= TxFifoEP2Data;
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TxFifoEmpty <= TxFifoEP2Empty;
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RxFifoEP0WEn <= 1'b0;
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RxFifoEP1WEn <= 1'b0;
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RxFifoEP2WEn <= RxFifoWEn;
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RxFifoEP3WEn <= 1'b0;
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RxFifoFull <= RxFifoEP2Full;
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end
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2'b11: begin
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TxFifoEP0REn <= 1'b0;
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TxFifoEP1REn <= 1'b0;
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TxFifoEP2REn <= 1'b0;
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TxFifoEP3REn <= TxFifoREn;
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TxFifoData <= TxFifoEP3Data;
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TxFifoEmpty <= TxFifoEP3Empty;
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RxFifoEP0WEn <= 1'b0;
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RxFifoEP1WEn <= 1'b0;
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RxFifoEP2WEn <= 1'b0;
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RxFifoEP3WEn <= RxFifoWEn;
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RxFifoFull <= RxFifoEP3Full;
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end
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endcase
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end
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endmodule
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