repo2/common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/writeUSBWireData.v
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//// ////
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//// writeUSBWireData.v ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// Module Description: ////
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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`include "usbSerialInterfaceEngine_h.v"
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`define BUFFER_FULL 3'b100
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module writeUSBWireData (
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TxBitsIn,
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TxBitsOut,
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TxDataOutTick,
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TxCtrlIn,
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TxCtrlOut,
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USBWireRdy,
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USBWireWEn,
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TxWireActiveDrive,
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fullSpeedRate,
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clk,
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rst
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);
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input [1:0] TxBitsIn;
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input TxCtrlIn;
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input USBWireWEn;
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input clk;
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input fullSpeedRate;
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input rst;
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output [1:0] TxBitsOut;
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output TxDataOutTick;
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output TxCtrlOut;
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output USBWireRdy;
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output TxWireActiveDrive;
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wire [1:0] TxBitsIn;
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reg [1:0] TxBitsOut;
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reg TxDataOutTick;
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wire TxCtrlIn;
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reg TxCtrlOut;
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reg USBWireRdy;
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wire USBWireWEn;
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wire clk;
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wire fullSpeedRate;
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wire rst;
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reg TxWireActiveDrive;
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// local registers
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reg [3:0]buffer0;
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reg [3:0]buffer1;
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reg [3:0]buffer2;
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reg [3:0]buffer3;
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reg [2:0]bufferCnt;
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reg [1:0]bufferInIndex;
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reg [1:0]bufferOutIndex;
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reg decBufferCnt;
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reg [4:0]i;
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reg incBufferCnt;
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reg fullSpeedTick;
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reg lowSpeedTick;
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reg fullSpeedRate_reg;
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// buffer in state machine state codes:
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`define WAIT_BUFFER_NOT_FULL 2'b00
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`define WAIT_WRITE_REQ 2'b01
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`define CLR_INC_BUFFER_CNT 2'b10
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// buffer output state machine state codes:
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`define WAIT_BUFFER_FULL 2'b00
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`define WAIT_LINE_WRITE 2'b01
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`define LINE_WRITE 2'b10
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reg [1:0] bufferInStMachCurrState;
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reg [1:0] bufferOutStMachCurrState;
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// buffer control
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always @(posedge clk)
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begin
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if (rst == 1'b1)
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begin
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bufferCnt <= 3'b000;
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end
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else
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begin
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if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
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bufferCnt <= bufferCnt + 1'b1;
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else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
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bufferCnt <= bufferCnt - 1'b1;
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end
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end
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//buffer input state machine
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always @(posedge clk) begin
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if (rst == 1'b1) begin
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incBufferCnt <= 1'b0;
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bufferInIndex <= 2'b00;
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buffer0 <= 4'b0000;
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buffer1 <= 4'b0000;
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buffer2 <= 4'b0000;
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buffer3 <= 4'b0000;
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USBWireRdy <= 1'b0;
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bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
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end
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else begin
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case (bufferInStMachCurrState)
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`WAIT_BUFFER_NOT_FULL:
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begin
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if (bufferCnt != `BUFFER_FULL)
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begin
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bufferInStMachCurrState <= `WAIT_WRITE_REQ;
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USBWireRdy <= 1'b1;
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end
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end
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`WAIT_WRITE_REQ:
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begin
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if (USBWireWEn == 1'b1)
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begin
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incBufferCnt <= 1'b1;
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USBWireRdy <= 1'b0;
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bufferInIndex <= bufferInIndex + 1'b1;
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case (bufferInIndex)
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2'b00 : buffer0 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};
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2'b01 : buffer1 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};
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2'b10 : buffer2 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};
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2'b11 : buffer3 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};
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endcase
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bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
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end
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end
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`CLR_INC_BUFFER_CNT:
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begin
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incBufferCnt <= 1'b0;
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if (bufferCnt != (`BUFFER_FULL - 1'b1) )
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begin
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bufferInStMachCurrState <= `WAIT_WRITE_REQ;
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USBWireRdy <= 1'b1;
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end
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else begin
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bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
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end
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end
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endcase
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end
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end
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//increment counter used to generate USB bit rate
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always @(posedge clk) begin
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if (rst == 1'b1)
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begin
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i <= 5'b00000;
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fullSpeedTick <= 1'b0;
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lowSpeedTick <= 1'b0;
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end
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else
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begin
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i <= i + 1'b1;
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if (i[1:0] == 2'b00)
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fullSpeedTick <= 1'b1;
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else
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fullSpeedTick <= 1'b0;
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if (i == 5'b00000)
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lowSpeedTick <= 1'b1;
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else
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lowSpeedTick <= 1'b0;
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end
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end
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//buffer output state machine
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//buffer is constantly emptied at either
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//the full or low speed rate
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//if the buffer is empty, then the output is forced to tri-state
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always @(posedge clk) begin
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if (rst == 1'b1)
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begin
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bufferOutIndex <= 2'b00;
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decBufferCnt <= 1'b0;
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TxBitsOut <= 2'b00;
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TxCtrlOut <= `TRI_STATE;
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TxDataOutTick <= 1'b0;
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bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
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fullSpeedRate_reg <= 1'b0;
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end
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else
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begin
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case (bufferOutIndex)
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2'b00: fullSpeedRate_reg <= buffer0[3];
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2'b01: fullSpeedRate_reg <= buffer1[3];
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2'b10: fullSpeedRate_reg <= buffer2[3];
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2'b11: fullSpeedRate_reg <= buffer3[3];
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endcase
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case (bufferOutStMachCurrState)
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`WAIT_LINE_WRITE:
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begin
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if ((fullSpeedRate_reg == 1'b1 && fullSpeedTick == 1'b1) || (fullSpeedRate_reg == 1'b0 && lowSpeedTick == 1'b1) )
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begin
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TxDataOutTick <= !TxDataOutTick;
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if (bufferCnt == 0) begin
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TxBitsOut <= 2'b00;
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TxCtrlOut <= `TRI_STATE;
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end
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else begin
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bufferOutStMachCurrState <= `LINE_WRITE;
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decBufferCnt <= 1'b1;
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bufferOutIndex <= bufferOutIndex + 1'b1;
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case (bufferOutIndex)
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2'b00 :
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begin
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TxBitsOut <= buffer0[2:1];
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TxCtrlOut <= buffer0[0];
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end
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2'b01 :
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begin
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TxBitsOut <= buffer1[2:1];
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TxCtrlOut <= buffer1[0];
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end
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2'b10 :
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begin
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TxBitsOut <= buffer2[2:1];
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TxCtrlOut <= buffer2[0];
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end
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2'b11 :
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begin
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TxBitsOut <= buffer3[2:1];
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TxCtrlOut <= buffer3[0];
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end
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endcase
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end
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end
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end
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`LINE_WRITE:
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begin
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decBufferCnt <= 1'b0;
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bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
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end
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endcase
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end
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end
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// control 'TxWireActiveDrive'
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always @(TxCtrlOut)
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begin
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if (TxCtrlOut == `DRIVE)
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TxWireActiveDrive <= 1'b1;
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else
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TxWireActiveDrive <= 1'b0;
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end
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endmodule
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